ĐĎॹá>ţ˙ šœţ˙˙˙’“”•–—˜™˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙ěĽÁ5@řż"ťbjbjĎ2Ď2 0Ŕ­X­X>p˙˙˙˙˙˙ˆ’ ’ ’ ’ * * * > â â â 8 tŽ ”> bÄv..... Žť4ďuĂwĂwĂwĂwĂwĂwĂ$ŘĆR*É4›Ă* ˛&  ˛&˛&›Ă’ ’ ..ŰÄ€D€D€D˛&’ l.* .uĂ€D˛&uĂ€D €DŒD:߇đ ţ ,* óĽ." ç‡ô˘Çâ Ä6ϑbůŠ|2Ä0bÄ1“Â^ÉŇ8P ^ÉóĽ> > ’ ’ ’ ’ óĽJ^É* =Śź *5°€DĺôŮ!Ů   ›Ă›Ă> > ¤ýâ "D^> > â Course Title:Academic WritingCourse Code:AWCourse Status:GenericRecommended Prior Study: Undergraduate degree or MastersLearning Outcomes: After completing the module the student should be able to: Communicate findings, in both written and oral form, in a professional manner Assess previous research reports/research papers completed in an area Critically appraise research data and assimilate, integrate and discuss in a logical way Produce an appropriate project description and specification Present and defend their findings clearlyAims & Objectives: To improve technical communication skills. To develop research and technical communication skills and awareness of the legal and ethical framework surrounding the activities of a professional engineer, including: personnel, health, safety, and risk (including environmental risk) issues. To enable students to demonstrate theoretical and practical research skills. To develop in students the ability to specify and design a major research project. To provide students with the opportunity to conduct and defend orally an independent research project.Syllabus Contents (Main topics): Introduction “Why do research”. On-line literature search methods. Interpreting your observations. Presenting your findings. Speaking and writing for the technical professions. Analysing observations and choosing appropriate means of presenting research findings. Introduction to search methods, technical writing and speaking.Assessment Procedure: Coursework: 40% Literature search & Research critique Coursework: 20% Presentation of proposed project. Coursework: 40% Detailed Doctoral Project proposal.Indicative Sources: Alison, B. (1997) 'The Students Guide to Writing Dissertations and Theses' Kogan Page Booth, V. (1993) 'Communicating in science: writing a scientific paper and speaking at scientific meetings' Cambridge University Press Galliers, R. (1994) 'Information Systems Research: Issues, Methods and Practical Guidelines' McGraw-Hill Education - Europe 187247439X Martin, M.W and Schinzinger, R (1997) 'Ethics in Engineering' 3rd McGraw-Hill 0-07-114195-2 Sharp, J.A. and Howard, K (1996) 'The management of a student research project' 2nd Gower Swetnam D (2000) 'Writing Your Dissertation: The Best Selling Guide to Planning, Preparing and Presenting First Class Work' How to Books Turk, C and Kirkman, J (1995) 'Effective writing' 2nd E & FN SponVan Wegenen, K.R. (1991) 'Writing a Thesis :Substance and Style' Prentice-Hall 0139710868 Course Title:Methodology of the Scientific ResearchCourse Code:MSRCourse Status:GenericRecommended Prior Study: Undergraduate degree or MastersLearning Outcomes: After completing the module the student should be able to: Demonstrate and develop fundamental research skills such as literature search, hypothesis/question formation, presentation of findings, and critical assessment of conclusions and implications To provide a theoretical background for conducting postgraduate work To provide a programme of training in the research processAims & Objectives: To enable students to demonstrate theoretical and practical research skills. To develop in students the ability to specify and design a major research project. To develop skills in planning, interpretation, analysis and data processing.Syllabus Contents (Main topics): Introduction to literature search methods including on-line methods. Interpreting and analysing your observations. Analysing observations and choosing appropriate means of presenting research findings. Science and scientific methodology: Epistemology, classification of research: theory development and testing; the deductive-inductive research process; and the role of independent and dependent variables. Data collection techniques: Observational Techniques; Survey Techniques; Experimental Techniques. Qualitative and quantitative data collection and analysis. Project planning, Time management and Gantt charts. Critical evaluation of published work Introduction to data analysis software (e.g. SPSS)Assessment Procedure: Continuous assessment: 25% Description of literature search rationale 25% Critical review of literature 25% Analysis and reflection on illustrative results 25% Suggested time management planIndicative Sources: Galliers, R. (1994) 'Information Systems Research :Issues, Methods and Practical Guidelines' McGraw-Hill Education - Europe 187247439X Gash, S. 2000. Effective literature searching for students. Gower. ISBN 0566081253 Sharp, J. A. And Howard, K. 1996. The management of a student research project (2nd edition). Gower. ISBN 056607706x Williamson, K. (2002) 'Research Methods for Students, Academics and Professionals :Information Management and Systems' 2nd Centre for Information Studies, Charles Sturt University, NSW 1876938420 Course Title:Legal Grounds and Structure of Doctoral ThesisCourse Code:LGSDTCourse Status:GenericRecommended Prior Study: Undergraduate degree or MastersLearning Outcomes: After completing the module the student should be able to: Formulate research proposals, and plan and conduct the five stages of empirical investigation: design, sampling, data collection, data processing, and reporting Demonstrate and develop fundamental research skills such as literature search, hypothesis/question formation, presentation of findings, and critical assessment of conclusions and implications produce an appropriate project description and specification Undertake a major research project and demonstrate competence in its executionAims & Objectives: To provide a theoretical background for conducting postgraduate work Formulate a research question of interest; apply relevant methods of investigation; and analyze, interpret and critically assess the findings. Gain knowledge and experience of the skills entailed in conducting research, including those concerned with literature searches, research design, fieldwork, statistical analysis, and report-writing. To develop in students the ability to specify and design a major research project. To provide students with the opportunity to conduct and defend orally an independent research project.Syllabus Contents (Main topics): Introduction “Why do research” Interpreting your observations. Project analysis and design Ethics in engineering, computing and technology Project planning Time management and use of Gantt charts Data collection techniques: Observational Techniques; Survey Techniques; Experimental Techniques. Structured presentation of research material Processes and procedures for dissertation submission and defenseAssessment Procedure: Coursework: 40% Outline of thesis structure and content Coursework: 20% Presentation of proposed project Coursework: 40% Detailed Doctoral Project proposalIndicative Sources: Alison, B. (1997) 'The Students Guide to Writing Dissertations and Theses' Kogan Page Galliers, R. (1994) 'Information Systems Research :Issues, Methods and Practical Guidelines' McGraw-Hill Education - Europe 187247439X Martin, M.W and Schinzinger, R (1997) 'Ethics in Engineering' 3rd McGraw-Hill 0-07-114195-2 Sharp, J.A. and Howard, K (1996) 'The management of a student research project' 2nd Gower Swetnam D (2000) 'Writing Your Dissertation: The Best Selling Guide to Planning, Preparing and Presenting First Class Work' How to Books Turk, C and Kirkman, J (1995) 'Effective writing' 2nd E & FN Spon Williamson, K. (2002) 'Research Methods for Students, Academics and Professionals :Information Management and Systems' 2nd Centre for Information Studies, Charles Sturt University, NSW 1876938420 Van Wegenen, K.R. (1991) 'Writing a Thesis :Substance and Style' Prentice-Hall 0139710868 Course Title:Intellectual Property ProtectionCourse Code:IPPCourse Status:GenericRecommended Prior Study: Undergraduate degree or MastersLearning Outcomes: After completing the module the student should be able to: Assess the essential contemporary legal, moral and ethical issues relating to intellectual property, as they concern the use of, and exploitation of, technology in the work environment. Examine the potential conflicts between EU IP rights, EU competition law, and National IP rights. Scrutinise the European Patents Convention and the workings of the European Patents Office. Evaluate the implications of Electronic Data Interchange and Cross-Border Data Flows in the EU.Aims & Objectives: Consideration and examination of intellectual property rights as they impinge on the exploitation of technology; rights, duties and responsibilities of inventors; licensees; employers and employees.Syllabus Contents (Main topics): Introduction and rational of Intellectual Property Rights Nature of Intellectual Property Law of Patent Industrial Designs Trade Marks and Trade Names Law of Confidential Information Copyright and Design Copyright Proposed EC Trade Mark European Patents Convention European Patents Office EDI and Cross Border Data FlowsAssessment Procedure: 100% coursework: A number of reports on ‘Case study’ examplesIndicative Sources: Phillips and Firth 'Introduction to Intellectual Property' Bainbridge, D. (2002) 'Intellectual Property' 5th Longman Dworki & Taylor (1988) 'Copyright, Design and Patents act' Blackstones Statutes Cornish, W. & Llewelyn, D. (2003) 'Intellectual Property :Patents, Copyright, Trade Marks and Allied Rights' 5th Thomson 0-421-78120-3 Holyoak, J and Torremans, P (2001) '''Intellectual Property Law''' 3rd Butterworths Bentley L. and Sherman B. (2004) 'Intellectual Property Law' 2nd OUP Course Title: Post Doctoral SeminarCourse Code:PDSCourse Status:GenericRecommended Prior Study: Undergraduate degree or MastersLearning Outcomes: After completing the module the student should be able to: Demonstrate and develop fundamental research skills such as literature search, hypothesis/question formation, presentation of findings, and critical assessment of conclusions and implications Present a seminar paper and respond appropriately to comments receivedAims & Objectives: Practice the skills involved in seminar presentation, including those required in effective summarizing of ideas and information, and oral communication. To develop research and technical communication skills and awareness of the legal and ethical framework surrounding the activities of a professional engineer, including: personnel, health, safety, and risk (including environmental risk) issues. To enable students to demonstrate theoretical and practical research skills. To develop in students the ability to specify and design a major research project.Syllabus Contents (Main topics): Introduction to search methods, technical writing and speaking On-line literature search methods. Interpreting your observations. Presenting your findings. Speaking and writing for the technical professions. Analysing observations and choosing appropriate means of presenting research findings. Science and scientific methodology: Epistemology, classification of research: theory development and testing; the deductive-inductive research process; and the role of independent and dependent variables. Data collection techniques: Observational Techniques; Survey Techniques; Experimental TechniquesAssessment Procedure: Presentation of a research seminar paper: 25% for the aural presentation 25% for the presentation (visual style and impact) 25% for the presentation (technical content) 25% for responses to questionsIndicative Sources: Booth, V. (1993) 'Communicating in science: writing a scientific paper and speaking at scientific meetings' Cambridge University Press Galliers, R. (1994) 'Information Systems Research :Issues, Methods and Practical Guidelines' McGraw-Hill Education - Europe 187247439X Turk, C and Kirkman, J (1995) 'Effective writing' 2nd E & FN Spon Williamson, K. (2002) 'Research Methods for Students, Academics and Professionals :Information Management and Systems' 2nd Centre for Information Studies, Charles Sturt University, NSW 1876938420 Course Title:Digital VLSI integrated circuitsCourse Code:DVICCourse Status:MainRecommended prior study: Basics of solid-state electronics CMOS technology Digital circuits and systemsLearning outcomes: Understanding of the advanced issues in electronic circuits and systems. Ability to use low-power design methods for digital electronic circuits and components. Understanding of theoretical and practical bounding of problems with regard to complexity and the ability to physically realize a circuit. Understanding of timing and synchronization methodologies for digital VLSI integrated circuitsAims & Objectives: This course aims to convey a knowledge of advanced concepts of circuit design for digital VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep submicron effects, interconnect, signal integrity, power distribution and consumption, and timing.Syllabus Contents (Main topics): VLSI models, logic implementation, properties, and abstractions. VLSI design systems, graphics systems, and design languages. Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits Clock distribution Low Power Design Voltage Scaling Power distribution Process Variations Timing Concepts Thermal DesignAssessment Procedure: The assessment is formed by 60% from lectures and 40% from laboratories and projectsIndicative Sources: Books/Papers: J. M. Rabaey, A. Chandrakasan and B. Nikoli, Digital Integrated Circuits: A Design Perspective, Second Edition, Upper Saddle River, NJ: Pearson Education, 2003. C. Piguet Ed, Low Power Electronics Design, CRC Press, 2004. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001. URLs (Web sites) http://www.seas.upenn.edu/~ese570/oldindex.html# anchor398319 http://www.cs.utah.edu/classes/cs6710/ Course Title:Digital systems design and implementationCourse Code:DSDICourse Status:Main Recommended prior study: Undergraduate background in digital systems.Learning outcomes: The course provides advanced knowledge and skills in selected topics in digital systems design and testing, as well as the methodology of research in this area. Students will be able to: Model digital systems at varying levels of abstraction; Synthesize and modify digital circuits described using a hardware description language using high-level design techniques and synthesis tools; Derive feasible and efficient testing and design-for-testability structures to achieve high quality and short design turnaround; Recognize trends, challenges and R&D opportunities in digital systems designAims & Objectives: The main objective is to provide an understanding of various aspects of digital system design and test. In particular, to look at how different design and test methodologies and styles are utilized to achieve high-performance, cost-effective designs. The course gives a novel view of digital system design and encourage students: To learn advanced techniques in the design of digital systems from specification and simulation to construction and debugging. To understand the limitations and difficulties in modern digital design.Syllabus Contents (Main topics): Design methodology and emerging technologies outlook. Design with simulation & synthesis in VHDL (Verilog) environment. Formal verification of digital systems Design for testability issues. Technology issues in implementation of digital systems in VLSI, Application Specific Integrated Circuits, and Field Programmable Gate Arrays. Reconfigurable digital system design basics Asynchronous design issues Systems on chip synthesis Power Management, System and Dynamic Power Management Design supporting automation environments Trends, challenges and R&D opportunitiesAssessment Procedure: 60% of the final mark is from an exam. 40% is from practical exercises, reports, and presentations. In place of some of the exercises, students undertake a literature survey of an area relevant to the course topics.Indicative Sources: Books/Papers: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, 3rd edition, 2004. Giovanni De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994. R. H. Katz, Contemporary Logic Design, Benjamin-Cummings/Addison-Wesley 1994. Michael D. Ciletti, Advanced Digital Design with the Verilog(TM) HDL, Prentice Hall,2004. Gary D. Hachtel and Fabio Somenzi, Logic Synthesis and Verification Algorithms, Springer, 2006. URLs (Web sites) http://venus.ece.ndsu.nodak.edu/ece/academics/ courses/ece375/s2004/ http://cslab.snu.ac.kr/course/cad04/ Course Title:Computer architecture and organizationCourse Code:CAOCourse Status:MainRecommended prior study: Digital System Design Computer Architectures Reconfigurable system design Operating SystemsLearning outcomes: After the course, students will be able to: Understand and apply the principles of Advanced Computer Architectures Research, design, and develop solutions for problems in computer and information systems.Aims & Objectives: This course is designed to provide information of state-of-the-art computer architectures.Syllabus Contents (Main topics): Topics include: Performance ISA Instruction-level paral-lelism (ILP) Thread-level parallelism (TLP) Dynamic scheduling Out-of-order execution Register renaming Exception handling Static scheduling (VLIW/EPIC) Cache/memory hierarchy design Speculation techniques Advanced branch predictor design Multiprocessor Coherency issues Storage systems Multicore processors Interconnection network Case studies including P6, Netburst, IA-64, x86-64 New trends in architecture / microarchitecture development.Assessment Procedure: Group project (implementation) 30%; Assignments (reconfigurable system design) 20%; Examination 50%.Indicative Sources: Books/Papers: J Hennessy and D. Patterson. Computer Architectures: A Quantitative Approach (3rd edition). Morgan Kaufmann 2002, ISBN 1-55860-596-7. Andrew S. Tanenbaum, Maarten van Steen, Distributed Systems: Principles and paradigms, Prentice Hall, 2002 URLs (Web sites) http://www.ece.eng.wayne.edu/~gchen/ece4680/ lecture-notes/lecture-notes.html http://williamstallings.com/ COA5e.html#anchor426312 Course Title:Embedded systems design and implementationCourse Code:ESDICourse Status: Main Recommended prior study: Undergraduate or postgraduate study of mathematics Undergraduate or postgraduate study of digital systems designLearning outcomes: Learn about system-level design of embedded systems. Develop the understanding of basic hardware/software co-design concepts. Familiarity with basic communication methods Gain design experience with case studies of embedded systemsAims & Objectives: Understand and comprehend embedded system design methods, computational models, design terminology. Analyze hardware/software tradeoffs, algorithms, and architectures to optimize the system based on requirements and implementation constraints To be able to specify a system and map the system specification on a chip architecture using CAD methods and tools that simultaneously handle both hardware and software, for modeling, partitioning, optimization and synthesis of the complete system. Understand the key problems of implementation of embedded systems. Syllabus Contents (Main topics): Hardware/Software codesign. Models of computation for embedded systems Specification and Modeling Behavioral synthesis Frameworks for modeling, simulation and codesign of embedded systems Hardware/software implementation Low power design Reconfigurable computing Core-based design Platform-based methodology Design examples and case studiesAssessment Procedure: 60% Exam, 40% AssignmentsIndicative Sources: Books/Papers: Readings in Hardware/software Codesign (The Morgan Kaufmann Series in Systems on Silicon) by Giovanni De Micheli, Rolf Ernst, and Wayne Wolf, 2001. Daniel D. Gajski, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000. Frank Vahid and Tony D. Givargis, Embedded System Design: A Unified Hardware/Software Introduction , Wiley; I.S.ed edition, 2001. D. D. Gajski, F. Vahid, S. Narayan, J. Gong, Specification and Design of Embedded Systems, Prentice Hall, Englewood Cliffs, NJ, 1994. URLs (Web sites) http://www.cs.ucr.edu/~vahid/courses/122a_f99/ index.html http://www.cse.unl.edu/~witty/class/embedded/ material.html http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/ http://www.cs.ucr.edu/~vahid/courses/122b_w02/ index.html Course Title:Computer NetworksCourse Code:CNCourse Status:MainRecommended prior study: Undergraduate course in computer networksLearning outcomes: At the end of the course a student will be able to: Understand the principles of present network architectures and protocols Understand the main ideas behind some of the current innovations in networking including, p2p protocols, wireless access systems, QoS, and network security Understand the limitations of the current Internet and its service model Critically read and review research papers in networking Perform an advanced research project on networkingAims & Objectives: This is an advanced course on computer networking. The goals are: Introduce basic and advanced concepts on network architectures and protocols Provide an understanding of technical details in a number of areas of networking Provide students with experience on critical reading and reviewing of research papers in networking Provide students with practical experience on performing an advanced research project on networkingSyllabus Contents (Main topics): The course is focused on understanding technical details in a number of areas of networking through reading and discussion of important research papers in the field. The topics which will be covered may include but are not limited to: Convergence of Voice and Data Networks Internet Architecture Network Protocols and Algorithms Wireless Networking Mobile Networking Quality of Service Network Security Network Performance Network Management Network Applications Assessment Procedure: Students will be required to submit at least two reviews of papers on the reading list. Students will also be required to submit a written research project plan, to review their progress with the instructor during the course and to submit the project at the end of the course. An oral presentation of the project results will also be required. Indicative Sources: Books/Papers: Computer Networking: A Top-Down Approach Featuring the Internet by Jim Kurose and Keith Ross, Addison-Wesley, 2004. TCP/IP Illustrated, Volume 1 by W. Richard Stevens. Addison-Wesley URLs (Web sites) http://www-static.cc.gatech.edu/classes/AY2007/cs6250_fall/ http://www.cs.jhu.edu/~terzis/cs644/syllabus.html http://web.cs.wpi.edu/~rek/Adv_Nets/Fall2006/ Fall2006.html Course Title:Advanced digital integrated circuitsCourse Code:ADICCourse Status:Specific - Area 1 Circuits, Devices, and ElectronicsRecommended prior study: Digital Schematic Technologies Software Engineering Learning outcomes: After the course, students will be able to understand and apply the principles for designing of digital systems with the advanced digital IC.Aims & Objectives: To be learned the advanced digital IC and to gain practical experience for their applicationsSyllabus Contents (Main topics): Main topics for advanced digital integrated circuits: Programmable logic devices /circuits Overview of programmable logic Design Technologies for programmable logic Synthesis of electronic systems Design intellectual property protection IC controlled by external programs Microcontrollers DSP (Digital Signal Processors) Microprocessors General-purpose processors Practical application of Advanced digital integrated circuitsAssessment Procedure: 60% of the final mark is from an exam. 40% is from practical exercises, reports, and presentations. In place of some of the exercises, students undertake a literature survey of an area relevant to the course topics.Indicative Sources: Books/Papers: VHDL Reference Manual, SYNOPSYS, inc., 1997. Armstrong J., Chip-level modeling with VHDL, 1991. A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS.  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Ulrich%20Heinkel" Ulrich Heinkel,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Martin%20Padeffke" Martin Padeffke,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Werner%20Haas" Werner Haas,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Thomas%20Buerner" Thomas Buerner,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Herbert%20Braisz" Herbert Braisz,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Thomas%20Gentner" Thomas Gentner,  HYPERLINK "http://www.amazon.com/s/ref=si3_rdr_bb_author/102-0595004-0788131?index=books&field%2dauthor%2dexact=Alexander%20Grassmann" Alexander Grassmann. John Wiley&Sons.Ltd, 2002. URLs (Web sites) http://bwrc.eecs.berkeley.edu/classes/icdesign/ ee241_s06/lectures.html http://www.cisl.columbia.edu/courses/spring-2002/ ee6930/reader.html Course Title:Analog, digital, mixed-mode circuitsCourse Code:ADMMCCourse Status:Specific - Area 1 Circuits, Devices, and ElectronicsRecommended prior study: Courses on semiconductor devices and electronic circuitry and logical designLearning outcomes: The following competencies will be developed: An understanding of the actual steps involved in the fabrication of an integrated circuit and design methodology. An understanding of advanced topics in design of analog circuits. The ability to combine digital and analog modules into the digital design flow. Aims & Objectives: To build upon the mathematical and engineering analysis background and provide the student with fundamental engineering knowledge about analog and digital electronic circuit design and analysis. To understand theory and to learn design of digital systems at transistor level. To understand the principles of VLSI CMOS digital design from a circuit and system perspective. To study power consumption and performance issues in nanometer CMOS circuits. Combine digital and analog modules into the digital design flow. Syllabus Contents (Main topics): Review of MOS and bipolar devices Deep Submicron CMOS, Silicon-on-Insulator, Strained Silicon, and other nanotechnology-era fabrication technologies. Logic design for high performance and/or low power. MOS design rules, interconnect design rules, supply design rules. Technology influence on design rules resistance effect, capacitance effect, propagation. Advanced topics in operational amplifier design. CMOS analog circuit modeling (SPICE modeling) Continuous-time and sampled-data filter implementations. Converter principles. Data converters. Mixed signal circuits (Digital-to-Analog Converter, Analog-to-Digital Converter) Mixed design. Power estimation/analysis techniques. ˇPower optimization techniques Emerging technologyAssessment Procedure: The assessment is formed by 60% from lectures and 40% from laboratories and projectsIndicative Sources: Books/Papers: N. H. E. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition) Addison Wesley; 2005. P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits (4th Edition), Wiley-IEEE Press, 2002. R. J. Baker CMOS Mixed-Signal Circuit Design, Wiley-IEEE Press, 2002. M. Rabaey, A. Chandrakasan and B. Nikoli, Digital Integrated Circuits: A Design Perspective, Second Edition, Upper Saddle River, NJ: Pearson Education, 2003. URLs (Web sites) http://www.ee.columbia.edu/%7Ekinget/EE6312_S06/ notes.html http://xanadu.ece.ucsb.edu/~long/ece594a/ ece594a.htm Course Title:Fiber optics and optical methodsCourse Code:FOOMCourse Status:Specific - Area 1 Circuits, Devices, and ElectronicsRecommended prior study: Graduate students in Computer Engineering, Computer Science or Electrical EngineeringLearning outcomes: Students will: Be familiar with the principles and technology of optical communication systems. Be able to design a point-to-point optical communications link, including power, noise and risetime/jitter budgets.Aims & Objectives: Provide students with the principles and technology of optical communication systems and fiber optics. Apply techniques learned to be able to design a point-to-point optical communications link.Syllabus Contents (Main topics): Overview of optical communication systems Optics and the characteristics of optical fibers Optical waveguides Digital communications Optical sources and transmitters Optical detectors and receivers Optical amplifiers Noise and detection Dispersion in optical communication systems Optical link designAssessment Procedure: 70% Exam, 30% AssignmentsIndicative Sources: Books/Papers: Fiber-Optic Communication Systems, 3rd Edition, by Govind P. Agrawal (Wiley) (ISBN: 0-471-21571-6) Optics, 4th Edition, by Eugene Hecht (Addison-Wesley) (ISBN: 0-8053-8566-5) Fiber-Optic Communications Technology, by Djafar K. Mynbaev and Lowell L. Scheiner (Prentice-Hall) (ISBN: 0-13-962069-9) Fiber Optic Commmunications, 4th Edition, by Joseph C. Palais (Prentice Hall) (ISBN: 0-13-895442-9) URLs (Web sites) http://cobweb.ecn.purdue.edu/~fsoptics/ opticscourses.htm http://www.utdallas.edu/~cantrell/ee6310/ IBM_Optical_Comm.pdf Course Title:Load management, Power Quality and ReliabilityCourse Code:LMPQRCourse Status:Specific - Area 1 Circuits, Devices, and ElectronicsPrerequisites: Information Technology Systems Power Quality Electrical Energy Protection Protection of StructuresLearning outcomes: On completion of this course the students should be able to: Information Technology Systems – consumer of Electrical Energy Methods and Devices for improvement of Power Quality Protection in Information Technology SystemsAims & Objectives: The aims of this course are: To explore theoretical and practical aspects of the Energy Efficiency of the Information Technology Systems. To explore evaluation of Power Quality. To design Electrical power protection. To design: Surge and Lighting Protection; Protection against Shock Currents; Overload Protection.Syllabus Contents (Main topics): Load Management & Energy Efficiency Control and Monitoring of Electrical Load and Consumption of Electrical energy in Information Technology Systems. Energy Efficiency on Information Technology Systems. Power Quality & Electrical Energy Protection Systems Voltage Characteristics in public Distribution Systems. The Anatomy of a Power Disturbance (Events, Causes, Effects). The Right Power Protection Solution for your Application. Control and Monitoring of Power Quality. Electrical Energy Protection Systems (Uninterruptible Power Supplies). Two simple Questions: 1. What Equipment needs protection. 2. What paths to and from that Equipment need Protection. The Steps of Protection: 1. Protect PC, Workstation, Peripherals and Data lines. 2. Protect PC and Workstation. 3. Protect Server Power. 4. Protect Internetworking/Telecom Power. 5. Protect Datacenter Power. 6. Secure your Network. 7. Customize and Manage Network Power Solutions. Efficiency of Electrical Energy Protection Systems. Surge and Lighting Protection in Information Technology Systems & Low-voltage installations Protection of Structures, General Principles. Protection against Surges caused by atmospheric Interferences. Protection against Lighting Electromagnetic impulse. Surge Protective Devices. Surge and Lighting Protection of Information Technology Systems. Surge Protective Devices for Information Technology Systems and Equipment. Protection against Shock Currents and Overload Protection Protective Measures against Shock Current. Protective Measures and Conditions for Disconnection. Overload Protection.Assessment Procedure: Written exam including a number of problems with a different degree of difficulty. The final mark is formed as a weighted average of the marks from the workshops and the exam.Indicative Sources: Books/Papers: Kyuchukov R. Effectity of Electrical Energy Protection Systems. Annual School Lectures, Sofia, 1999 Driver K. L. Understanding Harmonic Pollution and its negative Impact on Prifitability. Merlin Gerin, 1999 Ryan M. C. Power Quality Reference Guide. Ontario Hidro (2and Edition) Power Quality Mitigation Techniques Reference Guide. Rhonda Wright Industrial Business Markets Technology, Ontario Hidro Problems With Power Quality. Electric Power Research Institute, California, 1999 Coyle M. J. Coordinated Protection of AC and Data signal Systems. Power Quality Assurance. September/October 1997 The Problem with Power. Solution '99, American Power Conversion, July 1999 Mueller D. B. Roettger. Finding, Solving, and Learning from Power Quality Problems. Electrotek Concepts inc., 1997 Surge Protection, Explanatory Information. DEHN The truth of the matter is ... A straight Guide to Understanding Industrial Surge Protection Topics of Interest and Commonly Used Terms. MCG Surge Protection, 1998 Hofheinz W. Schutztechnik mit Isolationsuberwachung, Berlin, VDE Verlag gmbh, 1999 HD 384; IEC 60364. Electrical Installations of Buildings DIN V ENV 61024-1; DIN VDE 0185-103; E DIN VDE 0100 (Part 443); DIN V VDE 0100-534&1999-04. EN 50160. Power Quality. Course Title:Low-energy circuits and implementation architecturesCourse Code:LECIACourse Status:Specific - Area 1 Circuits, Devices, and ElectronicsRecommended prior study: Basics of solid-state electronics CMOS technology Digital circuits and systemsLearning outcomes: Understanding of the power issues in electronic circuits and systems. Ability to use low-power design methods for digital electronic circuits and components. Understanding of low-power architectures of electronic systems. Understanding of power analysis algorithms and computer-aided design tools. Aims & Objectives: The purpose of this course is to cover a variety of aspects related to low power digital design. While it is recognized that power consumption has become the limiting factor in keeping up with increasing performance trends, static or point solutions for power reduction are beginning to reach their limits. This course is intended to provide an insight into how various power reduction techniques can be used and orchestrated such that the best performance can be achieved within a given power budget, or the best power efficiency can be obtained under prescribed performance constraints. Syllabus Contents (Main topics): Quality metrics in digital design Power consumption in CMOS circuits Low voltage devices and dual-voltage systems Dual-threshold low leakage power devices Reducing dynamic power: transistor sizing, glitches, ASICs Power analysis: high level, logic simulation, probabilistic methods Logic families: pass-transistor, pseudo-nMOS, dynamic CMOS, domino CMOS Adiabatic and energy recovery logic Memories: power consumption and low power design Power-aware processors: benchmarking and low-power architectures Multi-core parallelism and low-power systems Power reduction in FPGA Clock distribution network and its power consumption Test power reduction methods Assessment Procedure: Exam (weighted 30% in final grade), presentation (30% in final grade) and the final report (40% in final grade)Indicative Sources: Books/Papers: J. M. Rabaey, A. Chandrakasan and B. Nikoli, Digital Integrated Circuits: A Design Perspective, Second Edition, Upper Saddle River, NJ: Pearson Education, 2003. C. Piquet, Low-Power Electronics Design, CRC, 2004 Chandrakasan, R. Brodersen, Low-Power CMOS Design, Wiley-IEEE Press, 1998. Main Journals – IEEE Trans. Computers and IEEE Trans. Circuits & Systems URLs (Web sites) http://www.engr.newpaltz.edu/~damu/spring_2007/ low_power.htm http://www.ece.ncsu.edu/asic/2005/lect05/ lowpower.htm Course Title:IP-based and Systems-on-chip DesignCourse Code:IBSCDCourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Computer Architectures Synthesis of Embedded Systems Analog and Digital DesignLearning outcomes: This program prepares students to meet the global career challenges in the next revolution in microelectronics, System-on-Chip Design, or Socware. This program provides the knowledge and skills needed for such integration work and the program bridges the computer engineering and microelectronics curriculums. Finishing this course the students should be able to: Design of heterogeneous System-on-Chip architectures. This includes custom hardware, microprocessors, and embedded software and operating systems, all on the same IC. Circuit level integration and implementation of heterogeneous blocks such as digital hardware, software, and analog interfaces while optimizing power consumption, performance, cost and noise. Design methodologies and CAD issues for specification, design and validation.Aims & Objectives: The program emphasizes design methods, architectures and circuit design towards system level integration on silicon. The aims and objectives of the overall curriculum are to give a solid background both for graduate studies and industrial employment. Students entering this program can have varying background.Syllabus Contents (Main topics): Embedded systems Design of Digital Integrated Circuits – LSI Digital Design using HDL SoC Architectures Intellectual Property Rights Electronic System Packaging Design of Digital Integrated Circuits – VLSI System Modelling Anatomy EDA CAD-Tools Radio Electronics Design of Fault-Tolerant Systems Low Power Analog and Mixed-signal Ics ASIC Design Methodologies Special Topics in SOCAssessment Procedure: Written exam including a number of problems with a different degree of difficulty. The final mark is formed as a weighted average of the marks from the workshops and the exam.Indicative Sources: Books/Papers: Wayne Wolf, Computers as Components: Principles of Embedded Computing System Design, Morgan Kaufman Publishers, 2005. William Dally and Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004. URLs (Web sites) http://www.ida.liu.se/~petel/architectures/ lecture-notes/lect5.frm.ps http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/ index.html Course Title:Digital systems testingCourse Code:DSTCourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Master degree knowledge and skills in computer architectures and digital logic design.Learning outcomes: The course provides advanced knowledge and skills in selected topics in digital systems testing, as well as the methodology of research in this area. Knowledge and understanding of the different design methodologies and styles for digital systems testing. Derive feasible and efficient testing and design-for-testability structures to achieve high quality and short design turnaround.Aims & Objectives: The main objective is to provide an understanding of various aspects of digital system testing. In particular, to look at how different design and test methodologies and styles are utilized to achieve high-performance, cost-effective designs. This course seeks to promote further learning and development efforts in the area of testing of digital systems.Syllabus Contents (Main topics): Defects, faults and errors in digital systems and their models. The main properties of faults: equivalence, dominance, redundancy, fault masking, conditions of fault activization, detectability of faults. Functional model of faults. Relationship between faults and tests. Hierarchical representation of faults and hierarchical synthesis of tests. Deterministic synthesis of tests for stuck-at-faults in combinational and sequential circuits at gate-level. Testing of multiple faults, avoidance of fault masking. Defect-oriented test generation for realistic physical defects. Delay testing. Generation of testprograms at register transfer and behavioral levels of abstraction. Hierarchical test generation. Evaluation of test quality. Parallel and deductive fault simulation, critical path analysis. Parallel critical path analysis. Hierarchical fault simulation. Fault diagnosis. Combinational and sequential methods of fault localization. Test compressing and optimization of test programs.Assessment Procedure: Exam (weighted 50% in final grade), assignments (20% in final grade) and the final report (30% in final grade)Indicative Sources: Books/Papers: Abramovici M., et al, Digital Systems Testing and Testable Design. IEEE Press, 2000 Bushnell, M.L., Agrawal, V.D., Essentials of Electronic Testing. Kluwer Academic Publishers, 2000 Bushnell, M.L., Agrawal, V.D., Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Boston: Springer, 2005 D. Gizopoulos, editor, Advances in Electronic Testing: Challenges and methodologies, Springer, 2006. URLs (Web sites) http://www.ida.liu.se/~zebpe/teaching/test/index.html http://www.caip.rutgers.edu/~bushnell/testbook.html Course Title:Formal methods in digital design and testCourse Code:FMDDTCourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Master degree knowledge and skills in computer architectures and digital logic design.Learning outcomes: This course covers topics in formal methods as used for digital hardware design, verification, and testing. Aims & Objectives: Student completing this course should: Be aware of different formal techniques used in hardware design and verification. Understand the distinction and relation between testing and formal verification. Understand how to model hardware circuits in a formal manner, thus enabling the use of verification. Understand specification languages for combinational and sequential circuits, including temporal logics. Understand different model checking techniques and how they apply to digital hardware.Syllabus Contents (Main topics): Modeling and formal reasoning about hardware using pencil-and-paper proofs refinement techniques Model checking Binary Decision Diagrams (bdds) applied to hardware circuits SAT-based verification Temporal logics (CTL, CTL*, LTL) Industry scale hardware verification Formal and semi-formal techniques in verification and validation.Assessment Procedure: 60% Exam, 40% AssignmentsIndicative Sources: Books/Papers: E.M. Clarke, O. Grumberg, and D.A. Peled, Model Checking, MIT Press, 2000.  (ISBN: 0262032708) T. Kropf, Introduction to Formal Hardware Verification, Springer-Verlag, 2000.  (ISBN: 3540654453) URLs (Web sites) http://www.cs.cmu.edu/afs/cs/project/calder/ papers/acm/acm.ps http://home.pacbell.net/ctchou/scu-cafm.html Course Title:Asynchronous designCourse Code:ADCourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Master degree knowledge and skills in digital logic design. Courses in computer organization and integrated circuit design are recommended.Learning outcomes: Understand and comprehend asynchronous design methods, computational models, design terminology. To be able to understand the pros and cons of synchronous versus asynchronous implementations of a system, and be able to systematically design and analyze such systems using state-of-the-art CAD tools. Methodology of research in asynchronous design.Aims & Objectives: This course aims at providing students with a thorough understanding of the theory and practice of specifying, designing and analyzing asynchronous or "clockless" systems. The course aims to provide students a front-line view of research of asynchronous design, to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.Syllabus Contents (Main topics): Introduction to asynchronous circuit design Synchronization problem Communication channels Communication protocols (handshaking expansion, data encoding, syntax-directed translation) Asynchronous pipelines Models (asynchronous finite state machines, Petri nets, timed event/level structures) Huffman circuits (solving covering problems, state minimization, state assignment, hazard-free logic synthesis) Muller circuits (complete state coding, hazard-free logic synthesis, hazard-free decomposition) Timing circuits Verification (circuit verification, protocol verification) Performance analysis/testing Case studies of real-world asynchronous processorsAssessment Procedure: Exam (weighted 30% in final grade), presentation (30% in final grade) and the final report (40% in final grade)Indicative Sources: Books/Papers: J. M. Rabaey, A. Chandrakasan and B. Nikoli, Digital Integrated Circuits: A Design Perspective, Second Edition, Upper Saddle River, NJ: Pearson Education, 2003. Sparso J. and Furber S. Principles of Asynchronous Circuit Design: a Systems Perspective. Boston: Kluwer, 2001. C. J. Myers, Asynchronous Circuit Design, John Wiley and Sons, July 2001. URLs (Web sites) http://ece.ut.ac.ir/Classpages/S86/ECE344/ http://bwrc.eecs.berkeley.edu/classes/icdesign/ ee241_s00/LECTURES/lecture25-asynch.pdf Course Title:Reconfigurable system designCourse Code:RSDCourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Introduction to digital designLearning outcomes: This course introduces methods and resources for hardware reconfigurable systems design. After completing the course, the student should know the concepts of FPGAs, the methods for hardware modeling and basic methods for building of FPGA-based reconfigurable systems.Aims & Objectives: The course is partitioned in to three parts and covers the main method for FPGA-based reconfigurable systems design. The course starts with a brief introduction in the nature of reconfigurable systems. After that education continues with introduction to FPGA chips and their architectural features. In the second part the course cover VHDL language as mean for behavioural description of digital hardware. The third part of course describes the implementation of two main methods used for partial reconfiguration of the FPGA chips. Syllabus Contents (Main topics): Introduction to Reconfigurable Systems PART A – FPGAs as means for building a Reconfigurable Systems FPGA fundamental Concepts The key thing about FPGAs. A simple programmable function. Fusible link technologies. Antifuse link technologies. FPGA architectures Configurable Logic Blocks, Look-up Tables, Fast carry chain, Embedded RAM, Embedded multipliers, Clock trees and clock managers. Configuring an FPGA Configuration files, Configuration cells, Antifuse-based FPGAs, SRAM-based FPGAs. Reconfigurable SRAM-based FPGAs SRAM cells, Using the JTAG port, Using an embedded processor. HDL- Based Design Flow HDL vs. Schematic-based design flow. Verilog HDL, VHDL, Mixed languages designs PART B – Design with VHDL Introduction to VHDL VHDL language abstractions, Design hierarchies, VHDL component, Entity and Architecture Behavioural Modelling Introduction to behavioural modelling, Transport vs. internal delay, Simulation details, Drivers, Block statement. Concurrent VHDL Signal assignment, Concurrency, WHEN statement, WITH statement, Data types, Vector assignment, Relational operators, Arithmetic operators. Sequential VHDL Concurrent and sequential data processing, Signal and variable assignment, Process statement, IF statement, CASE statement, NULL statement, WAIT statement, Loop statements, Asynchronous and synchronous reset. Library, Packages and Subprograms Libraries, Packages, Subprograms, Procedures, Functions, Resolution functions, Type conversion Structural VHDL Component declaration, Component specification, Port map, Generic map, Generate command Configurations Default configurations, Component configurations, Low level configurations, Entity-Architecture pair configuration PART C –FPGA Reconfiguration Methods Module-Based Partial Reconfiguration Defining Reconfigurable Modules Creating a Design for Partial Reconfiguration Bus Macro Communication Implementation Using Modular Design Difference-Based Partial ReconfigurationAssessment Procedure: ExamIndicative Sources: Books/Papers: Oldfield J., Dorf R., Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems, Wiley-Interscience, 1995 Clive "Max" Maxfield, The Design Warriors Guide to FPGA, Newnes, 2004 Sjoholm S., VHDL for designers, Prentice HaHall, 1997. Douglas L. Perry, VHDL : Programming By Example, McGraw-Hill Professional, 2002 URLs (Web sites) http:// HYPERLINK "http://www.xilinx.com" www.xilinx.com  HYPERLINK "http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf" http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf Course Title:Design supporting automation environmentsCourse Code:DSAECourse Status:Specific - Area 2 Digital System DesignRecommended prior study: Master degree knowledge and skills in digital logic design, computer organization and architecture, high-level language programming, and integrated circuit design. Learning outcomes: Proficiency in the use of computers and other modern tools to solve engineering problems. Develop mastery of various CAD programs, including schematic capture, simulation, hardware description languages, synthesis, and place and route tools. To be able to specify a system and map the system specification on a chip architecture using CAD methods. Understand how to interpret CAD tool outputs, and how to use the knowledge gained to improve the design.Aims & Objectives: The course aims to provide students a front-line view of computer aided digital design, development and applications: To be able to specify a system and map the system specification on a chip architecture using CAD methods and tools for modeling, partitioning, optimization and synthesis of the complete system. Have an ability to design and conduct experiments, as well as to analyze and interpret data. Understand the relevant factors in evaluating alternative system designs for a specific set of requirements.Syllabus Contents (Main topics): Hierarchical design concepts and technologies for digital circuits. Low-level design and modelling of digital circuits. CAD tools. Hierarchical design methods. Modelling and automatic synthesis of digital circuits using VHDL (Verilog). Design with CPLDs and FPGAs. Prototyping. Design with standard cells. Fault modelling and fault simulation. Digital logic testing and design for testability. Tests and project reviews.Assessment Procedure: Presentation (30% in final grade) and the final report (70% in final grade)Indicative Sources: Books/Papers: Mano and C.R.Kime, Logic and Computer Design Fundamentals, Third Edition, Prentice-Hall, Inc., 2004. H. Bhatangar, Advanced ASIC Chip Synthesis, Kluwer Academic Publishers, 2002. URLs (Web sites) http://www.csc.uvic.ca/~csc355/ http://www.ece.msstate.edu/~reese/EE4743/ http://www.ece.ncsu.edu/asic/2006/notes.htm Course Title:Advanced Computer ArchitecturesCourse Code:ACACourse Status:Specific - Area 3 Computer Systems Engineering and ControlsRecommended prior study: Introduction to computer architecture C/C++ programmingLearning outcomes: Students will understand principles and design of advanced computer architectures including advanced instruction level parallelism, thread-level parallelism, and application specific processors. Students learn and develop their skills from simulator design and quantitative analysis of experimental results.Aims & Objectives: This course is for graduate students to study techniques in high performance processor design. The course content includes both principles for modern superscalar processor design and research topics. Syllabus Contents (Main topics): Pipelined Processors Memory and I/O systems Superscalar Processor Design ILP Exploitation Advanced Speculation Techniques Thread-Level Parallelism Application-Specific ProcessorsAssessment Procedure: 60% Exam, 40% AssignmentsIndicative Sources: Books/Papers: Modern Processor Design: Fundamentals of Superscalar Processors by John P. Shen and Mikko H. Lipasti. McGrawHill, ISBN: 0-07-057064-7 Computer Architecture: A Quantitative Approach, 3rd Edition by John L. Hennessy and David A. Patterson. Morgan Kaufmann, ISBN: 1-55860-596-7 URLs (Web sites) http://www.doc.ic.ac.uk/~phjk/ AdvancedCompArchitecture/Lectures/ http://www.csee.umbc.edu/~younis/CMSC611/ CMSC611.htm#D  HYPERLINK "http://benchoi.info/Bens/Teaching/Csc521/index.htm" http://benchoi.info/Bens/Teaching/Csc521/index.htm Course Title:Dependability and fault toleranceCourse Code:DFTCourse Status:Specific - Area 3 Computer Systems Engineering and ControlsRecommended prior study: Master degree knowledge and skills in computer architectures and digital logic design.Learning outcomes: Understand the concepts of system reliability and availability, and their relationship to faults. Be aware of basic redundancy approaches to fault tolerance to improve system reliability and/or availability. Understand cost-dependability trade-offs and the limits of computer system dependability. Be aware of the subtle failure modes of "fault-tolerant" distributed systems, and the existing techniques for guarding against them.Aims & Objectives: To get insight in the aspects contributing to the dependability of computer based systems To learn the basic techniques to make system fault tolerant To assess and evaluate the dependability of systemsSyllabus Contents (Main topics): Dependability attributes (reliability, availability, safety, maintainability, confidentiality, integrity), impairments (faults, errors, failures), means (fault avoidance, fault tolerance, fault removal, fault forecasting). Techniques for fault tolerance hardware redundancy, information redundancy, software redundancy, time redundancy). Techniques to evaluate dependability. Testability as a property of the system under test, testability measures. Controllability and observability. Design for testability. (ad hoc methods of design for testability). Method of scan-paths. Boundary scan conception and standard. Methods of self-testing (self-test architectures, linear feedback shift register, functional self-test, software based self-test). Partitioning of systems on chip and global self-test planning. Test access mechanisms and strategies, sources and sinks. IEEE P1500 standard. Case studies of dependable components and systems (dependable processors, dependable power supply, dependable networks, dependable data storage and retrieval, and dependable computing systems). Assessment Procedure: 60% of the final mark is from an exam. 40% is from practical exercises, reports, and presentations. In place of some of the exercises, students undertake a literature survey of an area relevant to the course topics.Indicative Sources: Books/Papers: Mourad, S., Zorian, Y., Principles of Testing of Elevtronic Systems. J.Wiley & Sons, 2000. Abramovici et al, M., Digital Systems Testing and Testable Design. IEEE Press, 2000. Lala, P.K., Self-checking and Fault-Tolerant Digital Design, Morgan Kaufmann, 2001. Shooman, M.L., Reliability of Computer Systems and Networks, Wiley, 2002. Journals – IEEE Trans. Dependable and Secure Systems, IEEE Trans. Computers, IEEE Trans. Reliability, IEEE Trans. Software Engineering, ACM Trans. Computer Systems, and Information Processing Letters. Also, IEEE Computer, IEEE Micro, IEEE Design & Test of Computers. Conferences – Int’l Conf. Dependable Systems and Networks, Pacific Rim Int’l Symp. Dependable Computing, IFIP Int’l Working Conf. Dependable Computing for Critical Applications, Int'l Symp. Software Reliability Engineering. URLs (Web sites) http://www.cs.uidaho.edu/~krings/CS449/ http://www.ee.iastate.edu/~gmani/cpre558/ lecture_notes.htm Course Title:High performance systems and parallel processorsCourse Code:HPSPPCourse Status:Specific - Area 3 Computer Systems Engineering and ControlsRecommended prior study: Master degree knowledge and skills in computer architectures and digital logic design. Courses in integrated circuit design are recommended. Learning outcomes: Develop the understanding of basic parallel computing concepts. Linking parallel computing to other subfields of computer design. Be aware of the field of modern computer architecture design stressing parallel processing techniques. Develop the understanding of fault tolerance in parallel computing systems. Be aware of existing solutions to these two problems and be able to compare and contrast solutions based on criteria such as portability, efficiency, and scalability.Aims & Objectives: This course aims at providing students with understanding of the theory and practice of multiprocessor architectures and high performance networking. This course familiarizes the students with the background necessary for exploring the most effective ways of achieving parallelism. The course is a comprehensive study of parallel processing techniques and their applications from basic concepts to state-of-the-art parallel computer systems.Syllabus Contents (Main topics): Quantitative principles of computer design. Performance measures. Parallel computer models. Design of modern processor architectures. System interconnect architectures. Advanced techniques for exploiting instruction-level parallelism and their limits. Multiprocessors and thread-level parallelism. Pipelining. Memory hierarchy design. Supercomputer architecture. Comparison of serial, parallel and vector architectures. Fault tolerance in parallel computing systems. Emerging new technologies and research frontiersAssessment Procedure: Evaluation of the student’s activities during seminars, individual projects evaluation and face to face exam. Students are expected to write theoretical pert of the project as a conference or journal paper.Indicative Sources: Books/Papers: John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Fourth Edition (The Morgan Kaufmann Series in Computer Architecture and Design), 2006, ISBN: 0123704901. B. Parhami, Introduction to Parallel Processing: Algorithms and Architectures, Plenum Press, New York, 1999, ISBN 0-306-45970-1 K. Hwang and Z. Xu, Scalable Parallel Computing, McGraw-Hill, 1998, ISBN: 0-07-031798-4 Journals – IEEE Trans. Computers, IEEE Trans. Parallel and Distributed Systems, J. Parallel & Distributed Computing, Parallel Computing, Parallel Processing Letters. Conferences – Int’l Symp. Computer Architecture, Int’l Conf. Parallel Processing, Int’l Parallel & Distributed Processing Symp. URLs (Web sites) http://www.cs.bu.edu/~best/courses/cs551/lectures/ Menu.html http://www.cs.rit.edu/~ncs/parallel.html#courses Course Title:Fuzzy Logic and ControlCourse Code:FLCCourse Status:Specific - Area 3 Computer Systems Engineering and ControlsRecommended Prior Study: Undergraduate or postgraduate study of mathematics Undergraduate or postgraduate study of control systemsLearning Outcomes: After completing the module the student should be able to: Undertake reasoning in an domain with uncertainty using methods such as Bayesian Networks and Decision Networks Design and implement a fuzzy logic system for a real world scenario To gain experience in the methodology and practicality of applying fuzzy logic techniques.Aims & Objectives: Understand how to represent and reason about making decisions under uncertainty with methods such as Bayesian Networks and Decision Networks. To highlight the concepts of fuzzy logic and fuzzy mathematics, and create a fuzzy logic system applied to system control.Syllabus Contents (Main topics): Introduction to Knowledge based systems and rules. Decision making and classification. Building blocks of fuzzy systems (fuzzification by membership functions (MF); MF features - core, support, boundaries; MF types - triangular, trapezoidal, gaussian; MF assignment - intuition, inference, rank ordering; fuzzy inference - fuzzy logic, tautology, contradiction, equivalence, approximate reasoning; defuzzification - lambda cauts on fuzzy sets and relations, maximum, centroid, weighted average). Applications of fuzzy logic and systems (fuzzy rule bases - canonical forms, decomposition, aggregation; fuzzy modelling - interactions analysis, regression, training data sets; fuzzy simulation - partitioning, associative memories, relational equations, testing data sets; fuzzy control - stability analysis, optimisation, rule base decoupling, design). Fuzzy Logic as a method of Control. Adaptive Fuzzy Logic systems.Assessment Procedure: 40% Case study and literature survey in the field 60% Mini project on fuzzy logic design and implementationIndicative Sources: Books/Papers: Bandemer, H and Gottwald, S (1995) 'Fuzzy sets, fuzzy logic, fuzzy methods' Wiley 0-471-95636-8 Chen, G. and Pham, T., Introduction to Fuzzy Sets, Fuzzy Logic and Fuzzy Control Systems, CRC Press, 2001, 0849316588 Negnevitsky, M (2004) 'Artificial Intelligence: A Guide to Intelligent Systems' 3rd Edition Addison Wesley 0321204662 Ross, T.J. (1997) 'Fuzzy logic with engineering applications' McGraw-Hill 007114711X Russell, SJ and Norvig, P. Artificial Intelligence: A Modern Approach, 2nd edition. Prentice-Hall, 2003 ISBN: 0-13-790395-2 Tsoukalas, LH and Uhrig, RE (1997) 'Fuzzy and neural approaches in engineering' Wiley 0-471-16003-2 URLs (Web sites) http://homepages.cae.wisc.edu/~ece539/videocourse/notes/index.html http://www.austinlinks.com/Fuzzy/tutorial.html http://www.cs.surrey.ac.uk/teaching/cs364/ lecturenotes.html Course Title:Remote control systemsCourse Code:RCSCourse Status:Specific - Area 3 Computer Systems Engineering and ControlsPrerequisites: Basic knowledge in Boolean Algebra and Computer Systems.Learning outcomes: The students are informed about the “state-of-the-art” developments in remote control. They are familiar with different levels of security and quality of service and can design remote control systems.Aims & Objectives: The participants receive knowledge on the following areas of expertise: Remote Engineering and Future Trends Virtual and Remote Applications, Remote Control and Remote Sensing Control Systems and Automatic Control (fields of application) Telerobotics, Teleoperation of Mechatronic Systems Man Machine Communication Embedded Internet They can deepen their knowledge in various special modules, e.g. Mobile and Wireless Techniques Digital Image Processing Systems (hardware and software solutions, digital image capture and control)Syllabus Contents (Main topics): Virtual and Remote Applications, Remote Control, Remote Sensing (Graphical Programming, Physics of sensors, Lab Work) Control Systems and Automatic Control (Design of digital Control Systems, Validation of Parallel Control Systems, Lab work) Tele-robotics, Tele-operation of Mechatronic Systems (Advanced Control [Fuzzy, Neuro, Genetic], Lab work) Mobile & Wireless Techniques (Mobile Technologies, Wireless Internet) Digital Image Processing Systems: Hardware and software solution. Digital image capture and control Simulation technologies [Matlab Simulink] Signal processingAssessment Procedure: Pre test and post for every module, oral examinationIndicative Sources: Books/Papers: Fuzzy Control, Kevin M. Passino and Stephen Yurkovich, Addison Wesley Longman, Menlo Park, CA, 1998 (later published by Prentice-Hall). “Fuzzy Logic: a Practical Approach,” McNeill, Martin and Ellen Thro., 1994 Academic Press Professional. “Introduction to Fuzzy Systems”, G. Chen and T. T. Pham, , CRC Press, 2006 URLs (Web sites) http://www.crisp.nus.edu.sg/~research/links/rs-tut.html http://www.engineering.uiowa.edu/~aip/lectures.htm Course Title:Real-time systems designCourse Code:RTSDCourse Status: Specific - Area 3 Computer Systems Engineering and ControlsRecommended prior study: Computer Organization and Architecture Operating SystemsLearning outcomes: Specify the characteristics of real-time and safety critical systems. Identify architectural and design patterns for real-time and safety critical systems. Apply architectural and design patterns in the analysis and design of real-time systems. Model the structure of a real-time system. Describe hardware/software tradeoffs in the design of an real-time system.Aims & Objectives: The objective of the real-time systems course is to have students: Understand the concepts of real-time process and control Represent a real-time system using established methodologies Understand issues of time-critical computing Be familiar with a real-time operating system and application software Implement real-time system components Evaluate a design of a real-time system Do own research in the domain of real-time system developmentSyllabus Contents (Main topics): Basic concepts of real-time systems Requirements and design specifications. Derivation of real-time requirements from domain models. Scheduling in real-time systems Design patterns for real-time systems Language support for real-time systems Real-time taxonomy Safety critical systems Structural object analysis for real-time systems Modelling of real-time systems Performance measurements for real-time systemsAssessment Procedure: 60% Exam, 40% AssignmentsIndicative Sources: Books/Papers: Frank Vahid and Tony D. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley; I.S.ed edition, 2001. P. A. Laplante, Real-Time Systems Design and Analysis, Wiley-IEEE Press, 2004. B. P. Douglass, Real-Time Design Patterns: Robust Scalable Architecture for Real-Time Systems, Addison Wesley Professional, 2003. URLs (Web sites) http://data.uta.edu/~ramesh/cse5326-sp2000/ http://users.rsise.anu.edu.au/~shahab/Real Time Systems Course.html Course Title:Hardware/software co-designCourse Code:HSCDCourse Status:Specific - Area 4 Embedded Computer Systems and Signal ProcessingRecommended prior study: Master degree knowledge and skills in digital logic design and in computer architecture and organization. Learning outcomes: Develop the understanding of basic hardware/ software co-design concepts. Linking hardware/software co-design to embedded systems design theory and practice. Advances in hardware/software co-design, development of techniques and tools for automatic mapping of algorithms to hardware, availability of aids to the analysis and synthesis of complex systems.Aims & Objectives: Learn methodological design of digital signal processing systems. Understand and comprehend system design methods, computational models, design terminology. To be able to specify a system and map the system specification on a chip architecture using CAD methods and tools that simultaneously handle both hardware and software, for modeling, partitioning, optimization and synthesis of the complete system. Understand the key problems to further implement the embedded systems.Syllabus Contents (Main topics): 1. Hw/Sw Codesign of Embedded Systems: Introduction and Overview 2. Specification and Modeling Elements of a Model of Computation Common Models of Computation Languages Heterogeneous Modeling 3. Models of Computation - Formal Underpinnings Tagged Signal Model Kahn Process Networks DataFlow Process Networks Discrete Event Finite State Machines Codesign Finite State Machines Petri Nets 4. Graphical/Visual Specification Languages Dataflow Graphical Languages Statecharts (FSM): A Visual Formalism for Complex Systems 5. Frameworks for Modeling, Simulation and Codesign of Embedded SystemsAssessment Procedure: Exam (weighted 30% in final grade), presentation (30% in final grade) and the final report (40% in final grade)Indicative Sources: Books/Papers: Readings in Hardware/software Codesign (The Morgan Kaufmann Series in Systems on Silicon) by Giovanni De Micheli, Rolf Ernst, and Wayne Wolf, 2001. Daniel D. Gajski, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000. Frank Vahid and Tony D. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley; I.S.ed edition, 2001. URLs (Web sites) http://www.tik.ee.ethz.ch/tik/education/lectures/hswcd/ http://courses.cs.tamu.edu/rabi/cpsc689/ schedule.shtml http://www.ida.liu.se/~petel/codesign/ Course Title:Modeling and Synthesis of Embedded SystemsCourse Code:MSESCourse Status:Specific - Area 4 Embedded Computer Systems and Signal ProcessingRecommended prior study: Background in computer architecture and/or operating systemsLearning outcomes: Students will: Learn about system-level design of embedded systems comprised of both hardware and software. Investigate topics ranging from system modelling to hardware-software implementation. Explore analysis and optimization processes in support of algorithmic and architectural design decisions. Gain design experience with case studies using contemporary high-level methods and tools.Aims & Objectives: Understand the concepts, issues, and process of system-level design of embedded systems, i.e., hardware-software codesign. Use co-simulation to validate system functionality. Analyze the functional and nonfunctional performance of the system early in the design process. Analyze hardware/software tradeoffs, algorithms, and architectures to optimize the system based on requirements and implementation constraints. Describe architectures for control-dominated and data-dominated systems. Understand hardware, software, and interface synthesis. Describe examples of applications and systems developed using a codesign approach. Appreciate issues in system-on-a-chip design associated with codesign, such as intellectual property, reuse, and verification.Syllabus Contents (Main topics): Hardware/software systems and codesign Models of computation for embedded systems Behavioral design Architecture selection Partitioning, scheduling, and communication Simulation, synthesis, and verification Hardware/software implementation Performance analysis and optimization Design methodologies and tools Design examples and case studiesAssessment Procedure: 60% Exam, 40% AssignmentsIndicative Sources: Books/Papers: SpecC: Specification Language and Methodology by Daniel D. Gajski, Kluwer Academic Publishers, March 2000. F. Vahid and T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, John Wiley & Sons, 2002. D. D. Gajski, F. Vahid, S. Narayan, J. Gong, Specification and Design of Embedded Systems, Prentice Hall, Englewood Cliffs, NJ, 1994. J. Staunstrup and W. Wolf, editors, Hardware/Software Co-Design: Principles and Practice, Kluwer Academic Publishers, 1997. G. DeMicheli, R. Ernst, and W. Wolf, editors, Readings in Hardware/Software Co-Design, Academic Press, 2002 URLs (Web sites) http://technology.niagarac.on.ca/courses/ comp630/ http://www.ida.liu.se/~petel/codesign/lecture-notes/topics.frm.pdf Course Title:Evolutionary ComputationCourse Code:ECCourse Status:Specific - Area 4 Embedded Computer Systems and Signal ProcessingRecommended prior study: Basic programming skillsLearning outcomes: Understand the relations between the most important evolutionary algorithms presented in the course, new algorithms to be found in the literature now or in the future, and other search and optimisation techniques. Understand the implementation issues of evolutionary algorithms. Determine the appropriate parameter settings to make different evolutionary algorithms work well. Design new evolutionary operators, representations and fitness functions for specific practical and scientific applications.Aims & Objectives: Introduce the main concepts, techniques and applications in the field of evolutionary computation. Give students some practical experience on when evolutionary computation techniques are useful, how to use them in practice and how to implement them with different programming languages.Syllabus Contents (Main topics): Introduction to Evolutionary Computation Search Operators Selection Schemes Search Operators and Representations Evolutionary Combinatorial Optimisation Co-evolution Niching and Speciation Constraint Handling Genetic Programming Multiobjective Evolutionary Optimisation Learning Classifier Systems Theoretical Analysis of Evolutionary AlgorithmsAssessment Procedure: 100% ExamIndicative Sources: Books/Papers: Handbook on Evolutionary Computation, T. Baeck, D. B. Fogel, and Z. Michalewicz (eds.) IOP Press, 1997. Genetic Algorithms + Data Structures = Evolution Programs (3rd edition) Z Michalewicz, Springer-Verlag, Berlin, 1996 Genetic Programming: An Introduction, W Banzhaf, P Nordin, R E Keller & Frank D Francone, Morgan Kaufmann, 1999 Evolutionary Computation: Theory and Applications, X. Yao (ed) ,World Scientific Publ. Co., Singapore, 1999. (ISBN 3-540-65907-2) URLs (Web sites) http://www.cs.bham.ac.uk/~txs/teaching/2002/evo-computation/ http://www.cs.umt.edu/CS/COURSES/CS555/ lectures.html http://www.cs.uga.edu/~khaled/ECcourse/index.html Course Title:Image Processing and Recognition Course Code:IPRCourse Status:Specific - Area 4 Embedded Computer Systems and Signal ProcessingPrerequisites: Basic knowledge in Set Theory, Statistics & Probability Theory, Linear Algebra Functional Analysis. Basic programming skills (preferably in C/C++)Learning outcomes: Having completed the course, the students should: Apply sampling techniques to images and sounds. Posses basic audio/video pre- & post- processing methods, approaches and tools specific to pattern recognition (or classification) systems. Understand canonic classification theory and pattern recognition approaches on the base of sounds, images and video applications. Understand Harmonic and Wavelets Analysis basics – series, transforms, algorithms, domains, 1D, 2D, etc. Ability of thinking in object (time), frequency or wavelets domains, as well as in their correspondence. Ability of linking the stressed material with other areas like Control theory, Probabilities and Statistics, Computer Graphics, Vision & Tomography, etc. Ability to program simple application in C/C++ and/or MATLAB environment. Aims & Objectives: To introduce the theory of pattern recognition, starting from image processing and expending to both 1D signals (speech, handwriting, etc.) and 3D signals (video, ultrasonic, etc.), simultaneously discussing a number of application systems, for document analysis (e.g. OCR), automatic speech recognition, face recognition, biometrics and security, computer vision, etc.Syllabus Contents (Main topics): Image Processing and Computer Graphics dualities. 1D & 2D signal sampling. Harmonic analysis of signals (and images). Time (or object) and frequency domains of signal representation. Filters – linear and non-linear filters for 1D and 2D. Harmonic Analysis and Control theory dualities. Wavelets analysis. Harmonics and Wavelets dualities. Hough and Radon transforms’ dualities. Linear space of feature vectors. Most informative vector base. Principal component analysis. Invariant features. Classical recognition methods - probabilistic approaches, neural networks, hidden Markov models, syntactic approaches, comparison with DB of standards, some heuristics and combining principles. Setting-up approaches - Learning and Self-learning. Use cases – 1D, 2D, 3D cases; Audio-Video-Multimedia cases; Medical diagnosis; Biometrics; Content Based Image (or Object) Retrieval, etc. Assessment Procedure: 70% Final exam (35% written, 35% discussion) 30% Course project and home works.Indicative Sources: Books/Papers: Baxes G. A., Digital Image Processing - principles and applications, John Wiley Sons, Inc., NY, 1994. Duda R.O., P.E. Hart and D. G. Stork, Pattern Classification, John Wiley Interscience, 2000. Gonzalez R.C., and R.E. Woods, Digital Image Processing, Addison-Wesley Pub. Co., 1993. Haykin S., Neural Networks. Macmillan College Pub., Inc. 1994. Leondes C. T., Image Processing and Pattern Recognition, Academic Press, NY, 1998. Mallat S., Wavelet tour of signal processing, Academic Press, NY, 1999. Pratt W. P., Digital Image Processing, John Wiley & Sons, Inc., 2001. Rabiner L. R., Tutorial on Hidden Markov Models and Selected Applications in Speech Recognition, Proceed. of the IEEE, Vol.77, No.2, (1989), pp.257-286. Sonka M., V. Hlavac and R. Boyle, Image Processing, Analysis, and Machine Vision, 2-d edition, Brooks/Cole Publishing Co., CA, 1998. Strang G., and T. Nguyen. Wavelets and Filter Banks, Wellesley-Cambridge Press, 1996. Vaseghi S.V., Advanced Signal Processing and Noise Reduction, (2d ed.), John Wiley & Sons, Inc., NY, 2000. IEEE PAMI of last 5-10 years. URLs (Web sites) http://www2.cs.uh.edu/~shah/teaching/spring06/ notes.htm http://www.ece.wisc.edu/~hu/ece738/adim/outline.html Course Title:Speech ProcessingCourse Code:SPCourse Status:Specific - Area 4 Embedded Computer Systems and Signal ProcessingRecommended prior study: Undergraduate modules in AI or DSPLearning outcomes: Understand time and frequency domains and the Fourier Transform Understand the Convolution and Sampling Theorems Apply these techniques to digital images and sounds. An understand of speech production and speech waveforms Familiarity with current models of speech production and analysis Competence at implementing speech recognition algorithms Ability to program MATLAB scripts Ability to use HTK (Hidden Markov Model Toolkit) for speech recognition designAims & Objectives: To build upon foundation courses. To introduce the theory of pattern recognition and image processing. To present the characteristics of speech. To discuss automatic speech recognition systems.Syllabus Contents (Main topics): Sampling digital signals Impulses Convolution Fourier transform and properties Z-Transform and the pole-zero representation FIR and IIR filter design FFT processing and spectral analysis Speech Production, Representations and Terminology Introduction to Waveforms, Spectrograms, Fundamental Frequency and Formants Overview of ASR (Automatic Speech Recognition) and Trellis Algorithms Speech Parametrisation for ASR Assessment Procedure: 60% Written Exam, 40% ProjectsIndicative Sources: Books/Papers: DSP First - A Multimedia Approach (Edition 4th), JH McClellan, RW Schafer, MA., Yoder, Prentice Hall, 1998. Speech and Language Processing , Jurafsky, Daniel & Martin, James H., Prentice Hall, 2000 Discrete-time processing of speech signals , Deller, J. R., Proakis, J. G. & Hansen J. H. L., Macmillan, 1993 Speech synthesis and recognition , Holmes, J.N., Van Nostrand Reinhold, 1988 Fundamentals of speech recognition , Rabiner, L. & Juang, B.-H., Prentice Hall, 1993 Speech and Audio Signal Processing, Gold B. & Morgan N., Wiley, 1999 URLs (Web sites) http://www1.cs.columbia.edu/~hme28/ http://www.ee.ic.ac.uk/hp/staff/dmb/courses/speech/ speech.htm http://engr.smu.edu/ee/8373/lectures.html http://www.ifp.uiuc.edu/~hasegawa/notes/index.html Course Title:Interconnects and networks-on-chipCourse Code:INCCourse Status:Specific - Area 5 Networking and CommunicationsRecommended prior study: Master degree knowledge and skills in digital logic design. Courses in computer organization and integrated circuit design are recommended.Learning outcomes: Learn methodological design of Network on Chip based systems. Understand and comprehend Network on Chip design methods, computational models, design terminology. To be able to specify a system and map the system specification on a chip architecture. Understand the key problems to further implement the architecture as a Network on Chip.Aims & Objectives: The course aims to provide students a front-line view of network-on-chip research, develop and real applications; to prepare students for Ph.D. studies in these fields. It will also be a good pre-study for students who intend to continue a Ph.D. study in area of Digital Systems Design and Test. Syllabus Contents (Main topics): Introduction/ Survey/ Motivation Applications (Mapping, SoC, FPGAs, CMPs...) Architecture and Synthesis Disruptive Technologies Fault Tolerance/ Fault Models/ Error Detection Flow Control of NoC Traffic (Congestion Control) Formal Specification and Verification Latency Insensitive Design Power and Thermal Topics Routing Algorithms Run-Time Management The Timing Regime (Synchronous to Asynchronous) Industrial case studies of system-on-chip designs using the network-on-chip paradigm Assessment Procedure: Exam (weighted 30% in final grade), presentation (30% in final grade) and the final report (40% in final grade)Indicative Sources: Books/Papers: Jantsch and H. Tenhunen, ed., Networks on Chip, Kluwer Academic Publishers, 2003. Notes of Special Workshop on Future Interconnects and Networks on Chip, DATE'06, 2006. William Dally and Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004. A survey of research and practices of Network-on-chip, ACM Computing Surveys (CSUR)  HYPERLINK "http://portal.acm.org/toc.cfm?id=J204&type=periodical&coll=GUIDE&dl=GUIDE&CFID=1636071&CFTOKEN=90505649" \t "_self" archive Volume 38 , Issue 1, 2006 URLs (Web sites) On-Chip Network Research Resources Page http://www.cl.cam.ac.uk/~rdm34/onChipNetBib/ noc.html WWW Computer Architecture Page http://www.cs.wisc.edu/~arch/www/ Course Title:Network configuration and managementCourse Code:NCMCourse Status:Specific - Area 5 Networking and CommunicationsRecommended prior study: Undergraduate level courses in computer networks and theory of algorithms.Learning outcomes: Knowledge of fundamental concepts of configuration and management of computer communication networks. Knowledge of advanced routing and multilayer switching. Knowledge of methods and tools for network troubleshooting.Aims & Objectives: The main goals of this course is to develop in students: An advanced understanding of the fundamentals of computer networks, their configuration and management. Network simulation, and performance analysis and measurement. To develop advanced skills in network configuration management that allows one to control changes to the configuration of the network devices, like switches and routers. Students will be able to: Explain the issues for network management arising from a range of security threats. Summarize the strengths and weaknesses associated with different approaches to security. Develop a strategy for ensuring appropriate levels of security in a system designed for a particular purpose. Syllabus Contents (Main topics): Overview of network topologies and architectures Advanced routing. Route Optimization. Protocols supporting network and network device management. Protocols required on scalable networks. Design and configuration of networks that fulfill scalability. Emerging issues in networks data communications. Data security and integrity. Advanced study of networks troubleshooting. Quality of service issues: performance, failure recovery. Simulation. Performance analysis. Measurement.Assessment Procedure: 60% of the final mark is from an exam. 40% is from practical exercises, reports, and presentations. In place of some of the exercises, students undertake a literature survey of an area relevant to the course topics.Indicative Sources: Books/Papers: N. Olifer and V. Olifer Computer Networks: Principles, Technologies and Protocols for Network Design, John Wiley & Sons, 2006. Computer Networking: A Top Down Approach J.F. Kurose and K.W. Ross, Featuring the Internet (4th ed.), Addison-Wesley Longman, 2004. URLs (Web sites) http://users.cs.dal.ca/~zincir/cs6706.html http://www.csd.uwo.ca/courses/CS457a/notes/ http://www.comp.nus.edu.sg/~cs3103/ Course Title:Communications and network processorsCourse Code:CNPCourse Status:Specific - Area 5 Networking and CommunicationsRecommended prior study: Basic knowledge in the field of Computer network and communications.Learning outcomes: The course gives knowledge for using network processors in modern communication technologies.Aims & Objectives: The course aims are to introduce basic concept of using network processors in communication technologies. Fundamental concepts and architectures in the field of telecommunications and the role and functions of network processors are examined. General organization, architecture and application are considered.Syllabus Contents (Main topics): 1. A Profile of Network Applications. OSI Protocol Stack, Protocol Standards. 2. Generic functions of network processors. Kernel categories: pattern matching, lookup, computation, data manipulation, queue management, and control processing. 3. Network processors. 1. Intended data rate and applications Technical details of a network processor, target uses, data rates, types of layer processing. 2. Architecture Elements of the device –processing elements, description of specialized hardware, on-chip communication scheme, memory. 3. Interfaces Supported interfaces. 4. Programmability/Integrated Development Environment (IDE)/OS support Interface for users, Programming model, Integrated development environment, Operating systems support. 4. Analysis. 1. Architectures Special Functional Units, Timeline, Parallel Processing, Special Hardware, Integrated Co-processors. 2. Programmability Model, IDE, OS.Assessment Procedure: ExamIndicative Sources: Books/Papers: Crowley P., M.A. Franklin, H. Hadimioglu, Network Processor Design: Issues and Practices, Volume 1, Elsevier Science, 2003. Franklin M.A., P. Crowley, H. Hadimioglu, Peter Z. Onufryk, Network Processor Design: Issues and Practices, Volume 2, Elsevier, 2004. Franklin M.A., P. Crowley, H. Hadimioglu, Peter Z. Onufryk, Network Processor Design: Issues and Practices, Volume 3, Elsevier, 2005. Lekkas P.C., Network Processors: Architectures, Protocols and Platforms (Telecom Engineering), The McGraw Hill, 2003. Comer D.E., Network Systems Design with Network Processors, Agere Version, Prentice Hall, 2004. URLs (Web sites) http://www.cs.unc.edu/~jasleen/Courses/Spring03/ notes.html http://www.ecs.umass.edu/ece/wolf/papers/ arcs2002.pdf http://www-static.cc.gatech.edu/classes/AY2007/ cs8803hpc_fall/ Course Title:Pervasive ComputingCourse Code:PCCourse Status:Specific - Area 5 Networking and CommunicationsPrerequisites: Advanced computer architectures Modeling and synthesis of embedded systems Communication algorithms and networking protocols Broadband and mobile networksLearning outcomes: Finishing this course the students should be able to: Understand the fundamentals and principles of pervasive computing; Learn the recent developments in related technologies and research; Acquire hands-on application-building experience in multiple platforms; Analyse project’s or organisation’s requirements and choose appropriate wireless communication technologies and software environments; Design, develop and implement pervasive computing applications in different areas; Discuss the pervasive computing problems and solutions with other specialists.Aims & Objectives: The aims of this course are: To present the current technologies that form the new field of pervasive computing; To show the perspectives and some important research themes in pervasive computing; To equip students with knowledge and skills necessary to successfully take solutions and to implement pervasive computing in different areas.Syllabus Contents (Main topics): Introduction to Pervasive Computing Mobile Devices Wireless Technologies Mobile Networks Hardware Platforms for Pervasive Computing Research Software Architectures for Pervasive Computing Location and Context Awareness Pervasive Data access Programming Environments Security and Privacy in Pervasive Systems Human-computer Interaction in Pervasive Systems Assessment Procedure: 40% ex cathedra, 60% hands-on Written exam including a number of problems with a different degree of difficulty. The final mark is formed as a weighted average of the marks from the workshops and the exam.Indicative Sources: Books: Adelstein, F., S. Gupta, G. Richard, L. Schwiebert. Fundamentals of Mobile and Pervasive Computing: Essentials of Movable Data, McGraw-Hill Publishing, 2004. Hansmann, U., L. Merk, M. Nicklous, T. Stober, Pervasive Computing: The Mobile World, Springer, 2003. Malik M., Mobile and Wireless Design Essentials, Addison Wesley, 2003. Mattern, F., M. Naghshineh, Pervasive Computing: First International Conference, Pervasive 2002, Zurich, Switzerland, Springer- Verlag, 2002. Robinson, P., H. Vogt, W. Wagealla, Privacy, Security And Trust Within The Context Of Pervasive Computing, Springer Science+Business Media, 2005. Saha, D., A. Mukherjee, S. Bandyopadhyay, Networking Infrastructure for Pervasive Computing: Enabling Technologies and Systems, Kluwer Academic Publishers, 2003. Satyanarayanan, M., Pervasive Computing: Vision and Challenges. IEEE Personal Communications. Carnegie Mellon University. (2001). Steventon, A., S. Wright, Intelligent Spaces: The Application of Pervasive ICT, Springer-Verlag, 2006. URLs (Web sites) http://www-static.cc.gatech.edu/classes/AY2007/ cs7470_fall/  HYPERLINK "http://www.cc.gatech.edu/classes/AY2001/cs7470_spring/" http://www.cc.gatech.edu/classes/AY2001/ cs7470_spring/  HYPERLINK "http://www.computer.org/pervasive/" http://www.computer.org/pervasive/  HYPERLINK "http://www.cs.duke.edu/education/courses/cps296.3/fall00" http://www.cs.duke.edu/education/courses/ cps296.3/fall00 http://www.inf.ethz.ch/vs/events/dag2002/ Course Title:Broadband and mobile networksCourse Code:BMNCourse Status:Specific - Area 5 Networking and CommunicationsPrerequisites: Fiber optics and optical methods Interconnects and networks-on-chip Communication algorithms and networking protocols Computer networksLearning outcomes: Finishing this course the students should be able to: Acquired background to prepare for PhD thesis research in related areas; Understand network topology, layered architecture, protocols and technologies of current and emerging broadband and mobile networks; Understand the current practices and directions in this field; Analyse project’s or organisation’s requirements and choose appropriate broadband and mobile technologies; Provide broadband and mobile networks planning and optimisation; Design, develop and implement broadband and mobile networks in different areas;Aims & Objectives: The aims of this course are: To give suitable graduates an in-depth understanding of the technology, and the drivers for the technology, in the areas of broadband and mobile communications; To present various analytical methods and simulation tools that are used in the design and engineering of next-generation networks; To provide exposure of current research activities in these areas; To equip students with knowledge and skills necessary to successfully take solutions and to implement broadband and mobile networks in different areas.Syllabus Contents (Main topics): Broadband Networks: Architecture, Components, Protocols, and Standards. Mobile Networks – Architecture and Concepts; Cellular technology, GSM and GPRS 2.5G Wireless; 3G Wireless: UMTS, CDMA2000, WCDMA; 3.5G and 4G Wireless; WirelessLAN, WiMAX, Bluetooth, ad hoc Networks; Sensor Area Networks; Wireless Security.Assessment Procedure: 40% ex cathedra, 60% hands-on Written exam including a number of problems with a different degree of difficulty. The final mark is formed as a weighted average of the marks from the workshops and the exam.Indicative Sources: Books/Papers: Ahmad, A., Wireless and Mobile Data Networks, John Wiley & Sons, 2005. Anderson, H., Fixed Broadband Wireless System Design, John Wiley & Sons, 2003. Carty, G., Broadband Networking, Osborne, 2002. Correia, L., Mobile Broadband Multimedia Networks: Techniques, Models and Tools for 4G, Academic Press, 2006. Gaskin, J., Broadband Bible (Bible), Wiley, 2004. Ibe, O., Fixed Broadband Wireless Access Networks and Services, Wiley, 2002. Kahng, H., Information Networking. Networking Technologies for Broadband and Mobile Networks: International Conference ICOIN 2004, Busan, Korea, February 18-20, 2004, Springer, 2004. Lu, W., W. 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ƒpşpqˆqÇq2rsrĂrÄr×rőr–st]tőtôáááááᥚô‡‡‡‡$ & Fk¤$*$Ifa$gdŁ^I ¤x$Ifgd)Ł;kd s$$IfT–lÖ”˙;%§%ö§%ööÖ˙Ö˙Ö˙Ö˙4Ö laöŠT$ & Fj¤$*$Ifa$gdŁ^I $G$Ifgd‚6őtötu_uużuăuůu)v?vRvSvø¨¨¨¨¨¨¨¨l;kdşs$$IfT–lÖ”˙;%§%ö§%ööÖ˙Ö˙Ö˙Ö˙4Ö laöŠT$ & Fl$Ifa$gdŁ^I ¤x$IfgdŁ^I;kdms$$IfT–lÖ”˙;%§%ö§%ööÖ˙Ö˙Ö˙Ö˙4Ö laöŠT gvhvivjvˆv‰v8w9w:wLwMwNw\wz¸ż¸иťť ť ť ťťťťťťťťťťť ť!ť"ťíŰʚʚʚŰíۤš˘š¤šˆ„ˆ„ˆ„ˆ„}y}y„uqhDŸhŔg hÓ*E h­hÓ*Eha%˝jha%˝U#h-˙h5K5OJQJ^JmH sH U)h-˙ho556>*OJQJ^JmH sH  h-˙ho5OJQJ^JmH sH  h-˙hŁ^IOJQJ^JmH sH #h-˙ho55OJQJ^JmH sH #h-˙hVi5OJQJ^JmH sH "Svivˆv9w:wNw\wŁwňw"xxÂxyĆy¸U¸ôé۟ô”ƒƒƒƒƒƒƒƒƒ$ & Fm$*$Ifa$gdŁ^I $G$Ifgd‚6;kdt$$IfT–lÖ”˙;%§%ö§%ööÖ˙Ö˙Ö˙Ö˙4Ö laöŠT $$G$Ifa$gdKPK $G$IfgdKPK ¤x$Ifgd)Łohn Wiley & Sons, 2002. Ohrtman, F., WiMAX Handbook, McGraw-Hill Professional, 2005. Walke, B., Mobile Radio Networks: Networking, Protocols and Traffic Performance, John Wiley & Sons, 2001. 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„p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.h „S„äţĆS^„S`„äţo(‡hˆH.h „ „˜ţĆ ^„ `„˜ţ‡hˆH.’h „p„L˙Ćp^„p`„L˙‡hˆH.h „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.h „„˜ţĆ^„`„˜ţ‡hˆH.’h „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.h „°„˜ţĆ°^„°`„˜ţ‡hˆH.h „€„˜ţĆ€^„€`„˜ţ‡hˆH.’h „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.h„Đ„˜ţĆĐ^„Đ`„˜ţOJQJo(‡hˆHˇđh„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHoh„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đh„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđh„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHoh„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đh„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđh„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHoh„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đ7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.  „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.  „ „˜ţĆ ^„ `„˜ţ‡hˆH.’  „p„L˙Ćp^„p`„L˙‡hˆH.  „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.  „„˜ţĆ^„`„˜ţ‡hˆH.’  „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.  „°„˜ţĆ°^„°`„˜ţ‡hˆH.  „€„˜ţĆ€^„€`„˜ţ‡hˆH.’  „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.h„h„˜ţĆh^„h`„˜ţOJQJo(‡hˆHˇđ „S„äţĆS^„S`„äţo(‡hˆH.‚„„L˙Ć^„`„L˙.€„Ř „˜ţĆŘ ^„Ř `„˜ţ.€„¨ „˜ţƨ ^„¨ `„˜ţ.‚„x„L˙Ćx^„x`„L˙.€„H„˜ţĆH^„H`„˜ţ.€„„˜ţĆ^„`„˜ţ.‚„č„L˙Ćč^„č`„L˙.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7„S„äţĆS^„S`„äţCJOJQJaJo(‡hˆHˇđ7„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHo7„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đ7„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđ7„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHo7„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đ7„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđ7„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHo7„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đť„S„äţĆS^„S`„äţCJOJQJaJo(‡hˆHˇđť„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHoť„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đť„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđť„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHoť„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đť„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđť„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHoť„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „Đ„˜ţĆĐ^„Đ`„˜ţo(‡hˆH[]€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.h„Đ„˜ţĆĐ^„Đ`„˜ţOJQJo(‡hˆHˇđh „S„äţĆS^„S`„äţo(‡hˆH.h„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đh„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđh„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHoh„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đh„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđh„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHoh„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đh „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.h „ „˜ţĆ ^„ `„˜ţ‡hˆH.’h „p„L˙Ćp^„p`„L˙‡hˆH.h „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.h „„˜ţĆ^„`„˜ţ‡hˆH.’h „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.h „°„˜ţĆ°^„°`„˜ţ‡hˆH.h „€„˜ţĆ€^„€`„˜ţ‡hˆH.’h „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.  „h„¸˙Ćh^„h`„¸˙o(‡hˆH.  „ „˜ţĆ ^„ `„˜ţ‡hˆH.’  „p„L˙Ćp^„p`„L˙‡hˆH.  „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.  „„˜ţĆ^„`„˜ţ‡hˆH.’  „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.  „°„˜ţĆ°^„°`„˜ţ‡hˆH.  „€„˜ţĆ€^„€`„˜ţ‡hˆH.’  „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „¤„\ţƤ^„¤`„\ţo(„ „\ţĆ ^„ `„\ţo(.„ „0ýĆ ^„ `„0ýo(..„„0ýĆ^„`„0ýo(... „Ř „ČűĆŘ ^„Ř `„Čűo( .... „@ „ČűĆ@ ^„@ `„Čűo( ..... „„`úĆ^„`„`úo( ...... „x„`úĆx^„x`„`úo(....... „H„řřĆH^„H`„řřo(........7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.h„S„äţĆS^„S`„äţOJQJo(‡hˆHˇđh „8„˜ţĆ8^„8`„˜ţOJQJo(oh „„˜ţĆ^„`„˜ţOJ QJ o(§đh „Ř „˜ţĆŘ ^„Ř `„˜ţOJQJo(ˇđh „¨ „˜ţƨ ^„¨ `„˜ţOJQJo(oh „x„˜ţĆx^„x`„˜ţOJ QJ o(§đh „H„˜ţĆH^„H`„˜ţOJQJo(ˇđh „„˜ţĆ^„`„˜ţOJQJo(oh „č„˜ţĆč^„č`„˜ţOJ QJ o(§đh „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.h „ „˜ţĆ ^„ `„˜ţ‡hˆH.’h „p„L˙Ćp^„p`„L˙‡hˆH.h „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.h „„˜ţĆ^„`„˜ţ‡hˆH.’h „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.h „°„˜ţĆ°^„°`„˜ţ‡hˆH.h „€„˜ţĆ€^„€`„˜ţ‡hˆH.’h „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.„b„˜ţĆb^„b`„˜ţo(.€ „2„˜ţĆ2^„2`„˜ţ‡hˆH.‚ „ „L˙Ć ^„ `„L˙‡hˆH.€ „Ň „˜ţĆŇ ^„Ň `„˜ţ‡hˆH.€ „˘„˜ţƢ^„˘`„˜ţ‡hˆH.‚ „r„L˙Ćr^„r`„L˙‡hˆH.€ „B„˜ţĆB^„B`„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „â„L˙Ćâ^„â`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ť„Ö„ĺţĆ^„Ö`„ĺţCJOJQJaJo(‡hˆHˇđť„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHoť„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đť„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđť„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHoť„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đť„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđť„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHoť„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đ7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.  „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.  „ „˜ţĆ ^„ `„˜ţ‡hˆH.’  „p„L˙Ćp^„p`„L˙‡hˆH.  „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.  „„˜ţĆ^„`„˜ţ‡hˆH.’  „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.  „°„˜ţĆ°^„°`„˜ţ‡hˆH.  „€„˜ţĆ€^„€`„˜ţ‡hˆH.’  „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.Đ „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.Đ „ „˜ţĆ ^„ `„˜ţ‡hˆH.’Đ „p„L˙Ćp^„p`„L˙‡hˆH.Đ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.Đ „„˜ţĆ^„`„˜ţ‡hˆH.’Đ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.Đ „°„˜ţĆ°^„°`„˜ţ‡hˆH.Đ „€„˜ţĆ€^„€`„˜ţ‡hˆH.’Đ „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7„S„äţĆS^„S`„äţCJOJQJaJo(‡hˆHˇđ7„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHo7„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đ7„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđ7„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHo7„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đ7„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđ7„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHo7„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH. „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.  „h„¸˙Ćh^„h`„¸˙o(‡hˆH.  „ „˜ţĆ ^„ `„˜ţ‡hˆH.’  „p„L˙Ćp^„p`„L˙‡hˆH.  „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.  „„˜ţĆ^„`„˜ţ‡hˆH.’  „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.  „°„˜ţĆ°^„°`„˜ţ‡hˆH.  „€„˜ţĆ€^„€`„˜ţ‡hˆH.’  „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7„S„äţĆS^„S`„äţCJOJQJaJo(‡hˆHˇđ7„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHo7„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đ7„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđ7„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHo7„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đ7„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđ7„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHo7„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đ7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7„S„äţĆS^„S`„äţCJOJQJaJo(‡hˆHˇđ7„ „˜ţĆ ^„ `„˜ţOJQJ^Jo(‡hˆHo7„p„˜ţĆp^„p`„˜ţOJ QJ o(‡hˆH§đ7„@ „˜ţĆ@ ^„@ `„˜ţOJQJo(‡hˆHˇđ7„„˜ţĆ^„`„˜ţOJQJ^Jo(‡hˆHo7„ŕ„˜ţĆŕ^„ŕ`„˜ţOJ QJ o(‡hˆH§đ7„°„˜ţĆ°^„°`„˜ţOJQJo(‡hˆHˇđ7„€„˜ţĆ€^„€`„˜ţOJQJ^Jo(‡hˆHo7„P„˜ţĆP^„P`„˜ţOJ QJ o(‡hˆH§đ7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7„S„äţĆS^„S`„äţOJQJo(‡hˆHˇđ7„ׄ˜ţĆ×^„×`„˜ţOJQJ^Jo(‡hˆHo7„§ „˜ţƧ ^„§ `„˜ţOJ QJ o(‡hˆH§đ7„w „˜ţĆw ^„w `„˜ţOJQJo(‡hˆHˇđ7„G„˜ţĆG^„G`„˜ţOJQJ^Jo(‡hˆHo7„„˜ţĆ^„`„˜ţOJ QJ o(‡hˆH§đ7„焘ţĆç^„ç`„˜ţOJQJo(‡hˆHˇđ7„ˇ„˜ţơ^„ˇ`„˜ţOJQJ^Jo(‡hˆHo7„‡„˜ţƇ^„‡`„˜ţOJ QJ o(‡hˆH§đ7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.ý „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.ý „ „˜ţĆ ^„ `„˜ţ‡hˆH.’ý „p„L˙Ćp^„p`„L˙‡hˆH.ý „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.ý „„˜ţĆ^„`„˜ţ‡hˆH.’ý „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.ý „°„˜ţĆ°^„°`„˜ţ‡hˆH.ý „€„˜ţĆ€^„€`„˜ţ‡hˆH.’ý „P„L˙ĆP^„P`„L˙‡hˆH. „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH. „S„äţĆS^„S`„äţo(‡hˆH.€ „ „˜ţĆ ^„ `„˜ţ‡hˆH.‚ „p„L˙Ćp^„p`„L˙‡hˆH.€ „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.€ „„˜ţĆ^„`„˜ţ‡hˆH.‚ „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.€ „°„˜ţĆ°^„°`„˜ţ‡hˆH.€ „€„˜ţĆ€^„€`„˜ţ‡hˆH.‚ „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.h „S„Ş˙ĆS^„S`„Ş˙o(‡hˆH.h „ „˜ţĆ ^„ `„˜ţ‡hˆH.’h „p„L˙Ćp^„p`„L˙‡hˆH.h „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.h „„˜ţĆ^„`„˜ţ‡hˆH.’h „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.h „°„˜ţĆ°^„°`„˜ţ‡hˆH.h „€„˜ţĆ€^„€`„˜ţ‡hˆH.’h „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 „°„˜ţĆ°^„°`„˜ţ‡hˆH.7 „€„˜ţĆ€^„€`„˜ţ‡hˆH.’7 „P„L˙ĆP^„P`„L˙‡hˆH.7 „S„äţĆS^„S`„äţo(‡hˆH.7 „ „˜ţĆ ^„ `„˜ţ‡hˆH.’7 „p„L˙Ćp^„p`„L˙‡hˆH.7 „@ „˜ţĆ@ ^„@ `„˜ţ‡hˆH.7 „„˜ţĆ^„`„˜ţ‡hˆH.’7 „ŕ„L˙Ćŕ^„ŕ`„L˙‡hˆH.7 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