ࡱ> z\7 bjbjUU J7|7|όl&QQQQDVQ&ý2SSSSSjVktil<$ lqg.jllpSS}pppl&SSplppu <nSS @M&IQen*<n$0ýfpnp&&EE 210 - Lab #1 - Elementary Measurements. K. Dudeck In this lab you will become familiarized with the measurement of DC voltage and current for simple circuits. The ohmic relationship for resistors will also be verified experimentally as well as Kirchoff's circuit laws.  Part I. Ohm's Law Construct the circuit shown to the right. Use a decade box for the variable resistor, R. Use a DC power supply for the voltage, V. 1) Set the decade box for 100. Adjust the power supply to achieve 1V across the resistor, R. Measure and record the current through the resistor. By changing the decade box appropriately, also measure the current through each of the following resistors (decade box settings): 250 , 500, 1k, and 5k. 2) Adjust the power supply to each of the following voltages: 2, 3, 5, 9, and 10V, and repeat the measurements described in 1). Fill the measured current values for the table below. Voltage (V)Current (A)1002505001k5k135910 3) Make a graph with the current on the y-axis and the voltage on the x-axis. For each resistor, plot the current at each voltage and draw the best straight line through the data points. Calculate the resistance from the slope, where: 1/R =  I /  V . Part II. Kirchoff's Relationships. Construct the circuit shown to the right. Use fixed resistors for R1 and R2 (H"1k). Use the decade box for R3. 1) Measure the precise resistance values of the fixed resistors R1 and R2. Record these values. Set the power supply voltage to 10V. The current through R1, I, and the voltage across R3, VR3, will be measured for various values of R3 (R3= 0, 500, 1k, 2k, 10k, and 100k ). 2) Measure I and VR3 for the various values of R3. Calculate the current through R2, IR2, and the current through R3, IR3, by using the measured voltage and resistance. Do these currents add up to equal the current, I, entering the node? Fill in the values obtained, VR3, I, IR2, IR3, and IR3+IR3, in the table below. 3) For each value of R3, calculate the equivalent resistance, R23, of the parallel combination of R2 and R3. R23 = R2 | | R3 = (R2 R3) / (R2 + R3) Using voltage division, calculate the voltage that would be across the equivalent resistance, R23. How does this value compare to VR3? Add these calculated values to the table. V = 10V MeasuredCalculatedR3 ()VR3 (V)I (mA)IR2 (mA)IR3 (mA)IR2 + IR3 (mA)R23 ()VR23 (V)05001k2k10k100k Part III. AC Waveforms. 1) Calculate the RMS voltage of a sine wave with peak amplitude Vo, period T, and a DC offset Vdc. V(t) = Vo sin wt + Vdc 2) Calculate the RMS voltage of a triangle wave with peak amplitude Vo, period T, and no DC offset. V(t) = 4 Vo / T for 0 < t < T/4 3) Set a signal generator so that it has a sine wave output at a frequency of 200 Hz, and a amplitude of 1V (ground to peak ), use an O-scope to do this. 4) Measure the RMS voltage of this waveform using a) a digital VOM ( ex: Beckman ) b) an analog ( meter ) VOM ( ex: Simpson ) Is the RMS value .707 times the peak value? 5) Now add a DC offset to the sine wave, do this while looking at the O-scope. Measure the RMS values with both meters as in step 4). Do these measurements agree with your calculation step 1) ? 6) Adjust the DC offset while looking at the analog meter. You should notice a minimum needle deflection when the DC offset is zero. Repeat this procedure with the digital meter. How does the reading on the digital meter repond to an DC offset? 7) Select a triangle wave on the function generator with no DC offset and measure the RMS values as in step 4). Do these readings agree with the calculated values in step 2) ? 8) What conclusions can you draw from this exercise? EE 210 - Lab #2 - Digital-to-Analog Converter Introduction Digital-to-analog (D/A) converters are used in many real-world control and signal processing applications. For example, CD players use D/A converters to convert digital (sound/music) information that is read from the CD into an analog signal. In this lab, you will analyze and build a resistive circuit that converts digital information into analog information. You will begin the lab constructing and testing a four bit resistive R R/2 D/A converter. The D/A converter will be tested by applying 15V or 0V to each of the four inputs and comparing the measured output voltage to the expected output voltage (calculated in the Pre-Lab). In the second part of the lab, you will store four digitized waveforms in an erasable programmable read only memory (EPROM). The digitized waveforms include a sin(t), a sawtooth, a triangle, and a sin(t) + sin(2t). In the third part of the lab, the digitized waveforms stored in the EPROM will be used as the input to the D/A converter. Here, rather than considering only one input combination at a time, the digital input waveforms will vary as a function of time leading to time varying analog output waveforms. Finally, in the last part of the lab, you will study the effect of the number of digital output bits (e.g. 4 bit, 6 bit, 8 bit) on the analog output waveform. I. Resistive Network as a D/A Converter In this exercise, the 4-bit resistive R R/2 D/A converter that is given in Figure 1 will be analyzed, constructed, and tested.   II. Using EPROM as the Input to the D/A Converter In this exercise, you will use the digitized data that is being provided by the circuit board of Figure 4 as the input to your resistive D/A converter. The EPROM has 8-bits, therefore, for this part of the lab you should only use the four most significant bits as inputs to the D/A converter. Pre-Lab Exercise: Using nodal analysis, verify that VOUT = (VA + 2VB + 4VC + 8VD)/24 For a four bit R- R/2 D/A converter. Hint: Leave the matrix expression in terms of the unknowns VA, VB, VC, and VD. Once the matrix equation is written, multiply through by the appropriate constants, and subtract. In Class Exercise: Power down your circuit and disconnect the input voltages and the 20k load resistor form your 4-bit D/A converter. Connect the four most significant bits of the EPROM output to the input of the resistive D/A converter. Power up the EPROM circuit board by providing power, ground, and a 1 kHz clock signal using the waveform generator. Monitor the output of the D/A converter using the oscilloscope. Sketch carefully the waveform in your notebook. Label the voltage axis and the time axis. What do you notice about the smoothness of the output waveform? How could you make it smoother? Power down your circuit and insert a load resistor, RL = 20k, between the output and ground. How does the output waveform change from the case where no load resistor was connected between the output and ground? Is what you see in this part consistent with what you measured in Part 1 of the lab? III. 4, 6, or 8-bit D/A Converter In this exercise, you will add two or four more bits to the D/A converter to determine the effect of the number of digital output bits on the analog output waveform. In Class Exercise: Power down your circuit and disconnect the input voltages and the 20k load resistor from your 4-bit D/A converter. Add the resistors required to make your circuit a 6-bit or 8-bit D/A converter. Connect the six or eight most significant bits of the EPROM output to the input of the resistive D/A converter. Monitor the output of the D/A converter using the oscilloscope. Sketch carefully the waveform in your lab notebook. Label the voltage axis and the time axis. What do you notice about the smoothness of the output waveform? Is the waveform smoother then that you generated in Part 3? Why? EE 210 - Lab #3 - Oscilloscope Display of Electrical Conduction Characteristics Objectives: To assemble a curve tracer system using standard laboratory instruments, and obtain from it the conduction characteristics of an assortment of two-terminal devices. To adapt the display system to the measurement of the small signal resistance of a nonlinear device. Introduction: The performance of all electrical systems is based on the electrical conduction properties of their components, i.e. on how the flow of current depends on the voltage which produces it. For simple two-terminal devices, these characteristics are often presented in graphical for on an I-V curve. Graphical characteristics may be produced experimentally through point-by-point plotting of the locus of corresponding values of I and V as the excitation is varied over a desired range. Such methods, which would use an ammeter and a voltmeter, as shown below, can be very accurate, but can also be quite tedious.   The test circuit can be seen to be a single loop circuit, in which the sum of the voltage drops across the ammeter, the test device and the series resistance is equal to the voltage of the DC source. Actually, in this circuit, the ammeter could be omitted and the current could be calculated instead from the voltage drop across the known series resistance, using either a second voltmeter, or simply re-connecting the same voltmeter, which reads the device voltage. I. Curve Tracer Circuit  This is a simple adaptation of the circuit shown above. Instead of reading voltages with voltmeters placed across the device and the series resistance, we can use the input channels of a two-channel oscilloscope in its X-Y mode as shown in the diagram below. At any instant time the X and Y deflections of the spot form its quiescent position will be proportional respectively to the device voltage and to the device current, so the spot will trace out repetitively a replica of the I-V curve. The following considerations are important for a valid display: Each scope channel must be DC coupled so that the origin of the I-V curve is at a known, fixed point, usually at the center of the screen. The Y-channel of the scope should be in its inverted mode so that positive current flow produces a positive deflection on the Y-axis. For convenience, choose R = 10n ohms to facilitate calibration of the Y-axis in units of Amps/div. Use similar values of R for higher current devices. The two oscilloscope inputs share a common ground reference, so the swept voltage source (function generator) must be ungrounded, or floating. The waveform from the function generator must vary gradually (not stepwise) and so may either be sine or triangle. The repetition frequency of the function generator output should be as low as possible without causing unpleasant flicker in the display. This will minimize the current needed to charge and discharge the stray capacitance between the low side of the function generator and ground. This capacitance is in parallel with R and represents a circuit branch whose current has been ignored in the simple analysis of the system. This current will distort the display if not kept small. It is recommended that both the test device and the resistor, R, be mounted on BNC-binding post adapters at the oscilloscope inputs. This will minimize the amounts of scope input capacitance, which are in parallel with the test device and the current-sensing resistance, R. Switch the scope to its reduced bandwith mode (10MHz). This will minimize the pickup of high frequency noise, which tends to blur the oscilloscope trace. Experiment A Assemble the curve tracer circuit as described above, selecting R=1000 ohms. Insert an unknown resistor in the range of 100-10,000 ohms in the test position, and center the spot (function generator OFF). Switch the function generator ON, and note the linear I-V curve which results. Experiment with this using a very low (Sub-Hertz) sweep frequency so you can observe the spot executing its cylindrical pattern. Also use the DC OFFSET control of the function generator to develop asymmetrical sweep patterns. Develop a procedure for converting the slope of the trace to an equivalent value of resistance, and check the correctness of your procedure against the nominal value of the test resistor. Repeat this test with a second resistor of significantly different value. Record your observations and calculations in your notebook, and comment on the use of the curve tracer circuit as an ohmmeter. Be sure to include sketches of the display patterns. Experiment B Use the same curve-tracer system to examine the conduction characteristics of the following diodes (in each case connect the cathode of the diode to the grounded side of the test port.) IN4004 power rectifier diode (Reduce R to 10 ohms for this test) IN5234 6.2V zener diode (R = 100 ohms) Red LED (R = 1000 ohms) For each diode, make a careful labeled sketch of its conduction pattern, and arrange these three sketches in a vertical stack on your notebook page, using the same voltage scale for each. Comment briefly on the similarities and the differences among these three diode characteristics. Experiment C The diodes which you have examined are examples of nonlinear two- terminal devices. In later lecture courses you will study similar diode devices and learn to describe them also by algebraic equation models, which represent the same conduction characteristics which you have produced here graphically. Non-linear devices are inherently more cumbersome to describe than are linear devices like resistors, which need only a single electrical parameter (the resistance.) In many circuit applications however, a nonlinear device may be used under conditions which cause its voltage (and current) to vary over only a very small range of values. In such cases the relevant section of its I-V curve is approximately a straight line, as indicated on the diagram.  For this limited range the device may be modeled by its small-signal resistance R = V/I . You can set up this situation experimentally on your curve-tracer circuit by reducing the AC amplitude of the function generator to a low (minimum) value and using its DC OFFSET to locate the center of the scan at any desired point along the I-V curve. The linear segment which is displayed will probably be much too small for its slope to be measured at this time. However, you can zoom in on the segment by switching both scope channels to AC COUPLED (this will cause the segment to move to center screen) and then increasing the deflection sensitivity of both X and Y channels until the line segment is long enough to its slope to be measured. Use this method to measure the small signal resistance, r, of the IN4004 diode at bias currents of 10mA and 50mA. The theory of semiconductor diode connection predicts that the small signal resistance of a forward biased diode is inversely proportional to its DC bias current, i.e., r= 1/I, so r x I = constant. Use your experimental data to test this theory, and if you confirm it to be substantially true, evaluate the constant, expected to be of order 50mA. Experiment D: Input Conduction Characteristic of a TTL-NAND Gate (7400N) The curve tracer system can be used to display the I-V characteristics on any network port. The following setup is designed for a 7400 input port.  The circuit to the left of the dotted line is a modified, ungrounded source of sweep voltage. The diode restricts VIN to the positive values only, while the 30 resistance limits the maximum input voltage to above +3V. Otherwise, the system is the same as in Experiment B of this lab. Display the input conduction characteristic on the oscilloscope (THE +5DC SUPPLY MUST BE ON.)  The curve should appear generally as shown here. In the current logic HIGH state, the input current (IIH), is positive and quite small (a few microampheres typically) In the logic LOW state the input current (IIL), is negative (i.e. it flows outward) and has a value 1mA. The change from the HIGH to the LOW logic state occurs at about VIN=+1.5V, and is accompanied by a major change in input current. Compare your data with the TTL family specifications in the Data book. Also test whether strapping the two gate inputs together has any effect on the I-V curve. EE 210 - Lab #5 - Operational Amplifiers (Op-Amps) - Part 1 Introduction: In class, we defined a new device called the operational amplifier (op-amp). If you could look inside the package of an op-amp chip, you would find an integrated circuit that is comprised of over two dozen transistors and a dozen resistors. Luckily, you dont need to understand how the circuit functions (another class or two required) as long as you remember its equivalent circuit mode. In particular, in class you found that the function of the op-amp in a circuit can be modeled using a simple combination of resistors coupled with a dependent voltage source, as shown in Figure 1. Moreover, in order to analyze circuits that contain ideal op-amps it is even more straightforward just to apply the two golden rules that describe op-amp behavior with extreme (negative) feedback. The voltage difference between the input is zero (valid if A = "). 2. The inputs draw no current (valid if RIN = "). In this two-part lab, you will first consider the op-amp without feedback and verify that the open-loop gain A is very large. This will be followed by the construction of an inverting, non-inverting, and buffer amplifier. Throughout the lab, you will be asked to observe some of the non-ideal characteristics of the op-amp. These non-ideal characteristics include saturation of the output voltage and a finite frequency response. The Op-Amp Package: You will be using a LF412 dual op-amp for this lab. There are literally hundreds of op-amps available on the market today. Data books are filled with op-amps from such manufacturers as National Semiconductor and Texas Instruments. The op-amp comes in a sealed dual-in-line package (dip) as shown in Figure 2. When you look at the op-map form the top, the dot in the package designates pin #1. The circuit diagram that is shown in Figure 3 includes the power connections. Note that the diagram indicates the need for both positive and negative DC bias voltages (power for the internal transistor circuitry). In this lab, we will use VCC = +15V and VEE = -15V. The op-map will function with other supply voltages, however, for the LF412, the output will be limited to approximately VCC 1V and VEE + 1V. Using +/- 15V, this means that our maximum output will be limited to +/- 14V. You have to keep this in mind when designating your circuits! Finally, bypass capacitors (to be discussed later in the course) are included between the supply pins are ground to avoid noise that is common with many op-map circuits. Periodically throughout the lab, try pulling out the bypass capacitor and watch for noise on your output signal. Noise is not part of the theory, but it can kill you in the real world. Keep the notion of the bypass capacitor in the back of your mind for future use.      Exercise 1. Open Loop Circuit From the data sheet, we can determine that the op-amp has an open=loop gain (A is the equivalent circuit model) of 100,000 V/V for signals with low frequencies (see Open Loop Frequency Response figure on the data sheet). Without thinking about the consequences of such a large gain, you might connect an op-amp circuit in the following manner:   This is called the open-loop configuration (output NOT connected back to the input og the op-amp.) The op-amp is not usually used in the open-loop configuration, because the large gain causes saturation (clipping) of the output voltage for most reasonable input voltages. Let us verify that this is true by performing the following exercises. Pre-Lab question: Remember that the output is limited by the supply voltages (+/- 14 V output), calculate the maximum input voltage that can be applied to the op-amp before the output signal becomes distorted (reaches saturation or is clipped) for an input signal that has a frequency of 1kHz. From the figure that shows the open-loop frequency response of the amplifier as a function of frequency on the data sheet, it can be determined that the open-loop gain is approximately A = 100,000 for f = 100Hz, A = 3,000 for f = 1 kHz, and A = 300 for f = 10 kHz. Note: conversion 20 log A = gain in dB. In-Class Exercises: Use BNC to clip cables for Channel 1 and Channel 2 of the scope and for the LO output of the waveform generator. Using the oscilloscope, configure the waveform generator for a 1 kHz 50 mV peak-to-peak sinusoidal signal (+/- 25mV). Make sure that the DC OFFSET is zeroed. For most of the wavetek waveform generators, 50 mV peak-to-peak is the smallest output voltage that can be obtained. Note: Scope must be dc coupled. Using an LF412 op-amp in the open-loop configuration, build the circuit shown in Figure 4. Because this is a dual op-amp chip, you must choose either the A or B inputs and outputs. A voltage divider network us sued to attenuate the signal form the waveform generator by a factor of 10. Therefore, the input to the inverting terminal of the op-amp is 5mV rather than 50 mV. Monitor the input (across the waveform generator) and the output (between the output node of the op-amp and ground) of the circuit using the oscilloscope. Sketch the input and output waveforms as a function of time in your lab notebook (indicate the voltage and time scales). NOTE: Make sure that the invert button id not activated or the Channel 2 waveform will be flipped over. NOTE: Remember that the input voltage to the op-amp is a factor of 10 smaller than the measured input voltage (across the waveform generator). Increase the sinusoidal input voltage and observe the changes in the output voltage waveform. In your lab notebook, provide a description of the changes that you observed in the output voltage waveform for input voltages between 50 mV peak-to-peak and 1 V peak-to-peak. Questions: Calculate the voltage gain of the amplifier for input voltages that do not saturate the amplifier. Does the value you calculate correspond to the value of the open-loop gain found in the data sheet? What is the value of input voltage that saturates (results in clipping of) the output? Why do you see this saturation? Is the open-loop configuration useful for linear amplification of the input signals much greater than 5 mV? In-Class Exercises: With a 1V peak-to-peak input voltage, vary the frequency between 100 Hz and 10 kHz. Provide a description of the changes that you observed in the output voltage waveform for input frequencies between 100 Hz and 10 kHz. Questions: For which frequencies is the output signal linear (not distorted)? Why? Is the open-loop configuration useful for linear amplification? Why? Exercise 2. The Inverting Voltage Amplifier You verified in Exercise I that the open-loop configuration can not be used if a particular voltage gain (other than A that corresponds to the frequency on the input signal) is desired. The op-amp can be connected in a closed-loop configuration as shown in Figure 5, where the voltage gain is determined by the ratio of the resistors R1 and R2. this configuration actually amplifies and inverts the output voltage waveform relative to the input voltage waveform and is called an inverting amplifier.  Pre-Lab Questions: Design an inverting voltage amplifier that has a gain of  10 V/V. Choose R1 = 1 k and calculate the value of R2. What is the maximum input signal that can be applied before the output waveform becomes distorted (Remember the output will clip at +/- 14V)? In-Class Exercises: Using the oscilloscope, configure the waveform generator for a 1 kHz sinusoidal signal that has a magnitude (you choose) that is below the maximum value that you calculated in Pre-Lab Question #2. Connect a LF412 op-amp in the closed-loop inverting configuration as shown in Figure 5. Because this is a dual op-amp chip, you must choose either the A or the B inputs and outputs. Monitor the input (across the waveform generator) and the output (between the output node of the op-amp and ground) of the circuit using the oscilloscope. Sketch the input and output waveforms as a function of time in your lab notebook (indicate the voltage and the time scales). NOTE: Make sure that the invert button is not activated or the Channel 2 waveform will be flipped over. Increase the sinusoidal input signal until the output waveform saturates. Measure the input voltage at which this occurs. Once the output saturates, back off the input voltage until you achieve linear amplification again. Now pull out the bypass capacitors and monitor the output waveform. Put the bypass capacitors back into the circuit and make sure that the output is stable. Increase the frequency to 10 kHz and 100kHz. Measure that peak-to-peak output voltage at each frequency. Questions: Does the value of the voltage gain depend on the magnitude of the input signal? How does this compare with the op-amp in the open-loop configuration? What is the input voltage that saturates (clipping) the output? What is the point of the bypass capacitors? Does the value of the voltage gain change with increasing frequency? How does this compare with the open loop configuration? EE 210 - Lab #5 - Operational Amplifiers (Op-Amps) - Part 2 Introduction: In lab assignment #5 Part1, you connected the op-amp in the open-loop configuration and the closed-loop, inverting configurations. In this lab, you will continue your study of op-amps by considering the characteristics of a closed-loop, non-inverting amplifier, a unity gain amplifier, and a summing amplifier. Exercise 3. The Non-Inverting Voltage Amplifier The op-amp can be connected in a closed-loop configuration that results in an output that is not inverted, the circuit connection shown in Figure 6. In this case, the voltage gain VOUT/VIN is equal to 1 + R2/R1. Because the output voltage waveform is not inverted relative to the input voltage waveform, it is called a non-inverting amplifier. Pre-Lab Questions: Design a non-inverting voltage amplifier that has a gain of 4 V/V. Choose R1 = 1k and calculate the value of R2. What is the maximum input signal that can be applied before the output becomes saturated (remember that the output will clip at 14 V)? In-Class Exercises: Using the oscilloscope, configur3e that waveform generator for a 1 kHz sinusoidal signal with an amplitude that is less than the maximum value calculated in Pre-Lab Question #2. Connect a LF412 op-amp in the closed-loop, inverting configuration as shown in Figure 6. Because this is a dual op-amp chip, you must choose either the A or the B inputs and outputs. Monitor the input (across the waveform generator) and the output of the circuit (between the output node and ground) using the oscilloscope. Sketch the input and the output waveforms as a function of time in your lab notebook (indicate the voltage and times scales). NOTE: Make sure that the invert button is not activated or the Channel 2 waveform will be flipped over. Increase the sinusoidal input signal until the output waveform saturates. Measure that input voltage as which this occurs. Increase the frequency from 1 kHz to 10 kHz, 100 kHz and 1 MHz. Measure the peak-to-peak output voltage at each frequency. Questions: Does the voltage gain depend on the amplitude of the input signal? What is the input voltage that saturates (clips) the output? How does this compare with the value that you calculated in Pre-Lab Question #3? Does the value of the voltage gain change with increasing frequency? How does this compare with the op-amp in the open-loop configuration?   Exercise 4. The Unity Gain Amplifier (Buffer) Consider the following simple circuit that demonstrates the effect of circuit loading. The equivalent circuit model of the waveform generator is given by the circuit in the dashed box of Figure 7.   Pre-Lab Questions: What is the voltage VOUT if no load resistor is connected between nodes A and B (open circuit)? What is the voltage VOUT if a load of (a) RL = 10 k and (b) ) RL = 100  is connected between nodes A and B? In-Class Exercises: Using the oscilloscope, configure the waveform generator for a 1 kHz sinusoidal signal that has a peak-to-peak voltage of 2 V ( 1V). Measure the output voltage for VOUT of the waveform generator with no load connected (RL = "). Record the peak voltage measured between points A and B. Measure the output voltage VOUT when (a) a load resistance of RL = 10 k, and (b) a load resistance of RL = 100  is connected. Record the peak voltage measured between points A and B for both cases. Questions: If the resistor RL does not load the signal source, the voltage that you measure across the output will equal VIN. What does this exercise indicate about the effect that the load resistor RL on the voltage that you measure at the output on the circuit? Part B. Unity Gain Amplifier (Buffer Amplifier) In this part of the exercise, we will consider the design of a buffer stage that can be inserted in between the source and the load to eliminate the loading effect. Consider the circuit shown in Figure 8.   Pre-Lab Questions: We demonstrated in class that VOUT = VIN for the unity gain buffer amplifier. In addition to saturation at the supply voltages, the op-amp can only source 25 mA to the load (see output short circuit current on the data sheet). This will also limit the output voltage. To prove this, consider the following exercises. Calculate the current flowing through RL = 10 k for a VIN that is (a) 2 V peak-to-peak ( 1V) and for a VIN that is (b) 10 V peak-to-peak ( 5V). Will either of these input voltages cause saturation of the output? Calculate the current flowing through RL = 100  for a VIN that is (a) 2 V peak-to-peak ( 1V) and for a VIN that is (b) 10 V peak-to-peak ( 5V). Will either of these input voltages cause saturation of the output? In-Class Exercises: Insert the unity gain amplifier in the circuit of Figure 7 as shown in Figure 8. The waveform generator should still be configured for a 1 kHz sinusoidal signal that has a peak-to-peak voltage of 2 V ( 1V). Measure the output voltage VOUT with no load for VIN of 2 V peak-to-peak. Record the peak voltage measured between points A and B. Measure the output voltage VOUT with a load of RL = 10 k for a VIN of 2 V peak-to-peak. Record the peak voltage measured between points A and B. Increase the amplitude of the input voltage to 10 V peak-to-peak ( 5V) with a load of RL = 10 k. Sketch the input and output waveforms that you observed. Summarize the changes that you observed in increasing the input voltage from 2 V peak-to-peak to 10 V peak-to-peak. Measure the output voltage VOUT with a load of RL = 100  for a VIN of 2 V peak-to-peak. Record the peak voltage measured between points A and B. NOTE: In addition to clipping of the output voltage due to the limitation of the dc power supplies, the op-amp can only source 25 mA to the load (see output short circuit current on data sheet). This will also result in a saturation of the output waveform. To demonstrate this, try the following. Increase the amplitude of the input voltage to 10 V peak-to-peak ( 5V) with a load of RL = 100 . Sketch the input and output waveforms that you observed. Summarize the changes that you observed in increasing the input voltage from 2 V peak-to-peak to 10 V peak-to-peak. Questions: How do these output voltages differ from those you measured in Part A of this exercise when no buffer amplifier is included in the circuit? Why is the buffer effective in eliminating the loading effect of the circuit? At what voltage does the output waveform saturate due to the maximum output current limitations of the op-amp for a load of RL = 100 ? What limitations does this place on such buffer circuits? Exercise 5. The Summing Buffer Amplifier (level shifting)  In this exercise, the op-amp will be sued to build a summing amplifier. The output of a summing amplifier is a weighted sum of the input signal. This type of amplifier will be sued in the final project to implement a level shifting function. Pre-Lab Questions: For the amplifier sketched in Figure 9, choose the values of R1, R2, and R3 to implement the following function: VOUT = -VIN1 2VIN2 In-Class Exercises: Using the oscilloscope, configure the waveform generator for a 1 kHz sinusoidal signal that has a peak-to-peak voltage of 2 V. Apply the 5 V DC voltage to the input VIN1 and the 2 V peak-to-peak sinusoidal signal to input VIn2. Sketch the output signal as a function of time (label the voltage and time scales on your sketch). Adjust the peak-to-peak level of the sinusoidal input signal. Comment on the change in the output signal in your lab notebook (is there any change in the dc level of the output waveform?). Adjust the level of the DC input signal/ Comment on the change in the output signal in your lab notebook. EE 210 - Lab #6 - Field Effect Transistor and FET Amplifiers Objectives: To assemble a curve tracer system using standard laboratory instruments, as shown in a previous lab, to measure the Drain Curves for a MPF 102 N-Channel JFET. To measure the approximate VGS(off) and IDss parameters of the JFET. To calculate the Q-point of a Voltage Divider Biased JFET, build, and verify by measurement. To use this Biasing to construct a one stage, common source, JFET amplifier. Procedure: 1. Using the techniques learned in the a previous lab, V-I characteristics, obtain the Drain Curves for the MPF102 N-channel JFET shown below. Set the function generator to 10V P-P with a +5VDC offset, and a frequency of 100Hz. The DC offset is used to insure that the JFET operates strictly with positive voltages. Initially set the VGS power supply to 0V. Measure IDSS. Then increase (actually make more negative) VGS and determine VGSoff.  2. Using values of IDSS = 15mA and VGSoff =-2V, calculate the Q-point, (ID, VGS) for the voltage divider bias shown below. 3. Connect the circuit shown below and measure the Q-point. Make sure the VGS is in fact negative.  4. With the DC Q-point designed and verified, provide a way to have a small AC sine wave input swing the Q-point and cause a larger Voltage to appear on the output. This is accomplished with the circuit below. This circuit is called a Common Source JFET Amplifier. It does not have as much voltage gain as a Bipolar Transistor Amplifier, but has very high input impedance which makes it useful as the front end stage of a measuring instrument, or a radio receiver.  The 1uF and 10uF capacitors block the DC bias from escaping from the JFET but allow the AC sine wave to pass through and cause the amplification. Add the capacitors to your circuit and set the Vin function generator to 0.5Vp-p, 1000Hz sine wave. Verify this with the oscilloscope. Then with RL open, infinite resistance, measure Vout. Simultaneously display both Vout and Vin on the oscilloscope. The Voltage Gain is the ratio Vout/Vin. Notice that the two signals are out of phase with each other. 5. Here is an approximate way to measure the amplifiers output, Thevenin, resistance. Connect a variable resistor, RL, to the output of the amplifier. Vary the resistance until the output voltage is approximately half of the open circuit voltage. In theory, this occurs when RL equals the internal Thevenin resistance of the amplifier. Disconnect RL, and measure its resistance with an ohmmeter. Figure 1. Resistive R  R/2 D/A Converter  EMBED PBrush   EMBED Word.Picture.8   EMBED Word.Picture.8  Figure 1  Equivalent circuit model of the op-amp. For most op-maps, Ri is approximately 1 M and A is approximately 100,000 V/V (at low frequencies). The ideal op-amp assumes Ri = " and A = " (simplifies circuit analysis while providing good accuracy).  EMBED Word.Picture.8  Figure 2  Dual-in-line package (DIP) along with the pin-out of the LF412 dual op-amp.  EMBED Word.Picture.8  Figure 3 Circuit diagram for an op-amp including dc power connections. The bypass capacitors are included to reduce the noise that is present in the circuit.  EMBED Word.Picture.8  Figure 4 Open-loop configuration. Output of the op-amp is not connected to the input  EMBED Word.Picture.8  Figure 5 Closed-loop (output connected to the input) inverting op-amp configuration.  EMBED Word.Picture.8  Figure 6 Closed-loop (output connected to the input) non-inverting op-amp configuration.  EMBED Word.Picture.8  Figure 7 Circuit that demonstrates the loading effect.  EMBED Word.Picture.8  Figure 8 Circuit that contains a unity buffer amplifier to eliminate the loading effect.  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B2  3  <B   # r ! 6 B2 " 3 <B #@ # r $ 6 B2 % 3 <B &@ # <B ' # <B ( # <B )@ # <B * # <B + # @<B , # @<B - # @<B . # @<B / # @<B 0 # @<B 1 # @H2 2 C  H2 3 C  <B 4 # @ <B 5 # @ <B 6 # @ <B 7 # @<B 8 # <B 9@ # <B : # <B ;@ # <B < # <B =@ # <B > # <B ? # B S  ?  !"#$%&'()*+,-./0123456789:;?%D&t>%&t=RSt<a&t;dRt: ast9Rt8%at7> z ? t6 (t5  Wt4  t3h \ t2 \ k t1 ( t0> t/7 M t.%W&t-7W4Xt,%&pt+7p4qt*/ ; \ < t)  z  t( t' t& Ut%Ut$5gt#  U t"U\  t!M 5. t  F t\  tM i. tpFqtCt4itWFXt*titct WWtR~tW3tYWttStWtF|r t Fr8t St C&3Rt t FWrt1 t 'th FXrth XtM  t= 9- et(<=JK(=>JKRSUVXY\]opst::::::::@((`h(@UnknownGzTimes New Roman5Symbol3& zArial?5 zCourier New"qh{J{J!20l2 Ken Dudeck Ken Dudeck  FMicrosoft Word Picture MSWordDocWord.Picture.89q  FMicrosoft Word Picture MSWordDocWord.Picture.89q  FMicrosoft Word Picture MSWordDocWord.Picture.89qWordDocumentSummaryInformation(DocumentSummaryInformation8_1034507883 F@OMXM7 bjbjUU 7|7|=Ll<<<<< H<#hhhhh!!!"""""""$ $ ,&R"! !!!""hh""""!(thh""!"""""h\ LN?@<<%"p"""0#"~&"~&"". d Av + - i R v d o v + - - + - v v + <=>@BDEGHJKMOQSUVXY[]_`bcefhiklnprtvwyz|}B*CJOJQJ^JaJphB*CJOJQJ^JaJphB*CJOJQJ^JaJphB*OJQJ^JphjUmHnHu0=?@CDFGIJLMPQTUWXZ[^_abdeghjk=kmnqruvxy{|~N N!]"]# $ %Oh+'0l   ( 4 @LT\dss Ken Dudecken en Normale Ken Dudeck2n Microsoft Word 9.0@@Jf?@@Jf?@՜.+,0 hp  Penn State Hazleton  Title1Table`CompObj hObjInfo ObjectPool!XMXM      C"#$%&'()*+,-./0123456789:;<=>?@A^EFGHIJKLMOPQRSTUWXYZ[\]y`abcdefghijklmnopqrstuvwx|}~ i0@0 Normal_HmH sH tH <A@< Default Paragraph Font 48<FYpsvy|      48<FYpsvy|  @Vl,2$oT(/d6D(@H  (  <2  # r  6 r  6 r  6 r  6 r  6 r   6 r   6 r   6 r   6   r   6   r  6   r  6   r  6    r  6  r  6  r  6  <  #  B  3 B  3 B  3 B  3 B  3 B  3 B  3 B  3 6   B S  ?  t/ tn t Qt t5/t5nt5Qt5t 5 t  t 2]t qt t   t 2 ]t  q t   t < t _ t Jttn tKP{t9tt t@c`@UnknownG:Times New Roman5Symbol3& :Arial7& rDigital"hJ&JF!r0l2 Ken Dudeck Ken DudeckWordDocumentSummaryInformation( "DocumentSummaryInformation8_10345096133% FXMXM7 bjbjUU 7|7|l   @@@@@ L@lllll___$ R _1.___ll _l l_^ l` :qC@@o0`` 2 Output A Inverting Input A Non-Inverting Input A V- V+ Output B Inverting Input B Non-Inverting Input B 1 2 3 4 8 7 6 5 $&79NPRTVX`bsuB*CJOJQJaJphjUmHnHu"%&89OPSTWXabtuN N!7"7#"$"%Oh+'0l   ( 4 @LT\dss Ken Dudecken en Normale Ken Dudeck2n Microsoft Word 9.0@@r:qC@r:qC՜.+,0 hp  Penn State Hazleton  Title1Table!@CompObj$'hObjInfoObjectPool&)XMXM i0@0 Normal_HmH sH tH <A@< Default Paragraph Font  #26:JSVYbj{6  -./0123456789:;<=>?@AIJZ[  #26:JSVYbj{ 6 @V6kmnpqstvwyz|}#$'(*+-.01370000000000000000000000000000000006J*65lmn,2$ɖ~!260Zz@#km#(  r  6i B2  3 h<B  # gr  6f B2  3 e<B  # dr   6c B2   3 b<B   # ar   6` B2   3 _<B @ # ^r  6] B2  3 \<B  # [<B  # Z<B  # Y<B @ # X<B  # Wr  6V B2  3 U<B  # T<B  # S<B  # R<B @ # Q<B  # Pr  6O B2  3 N<B  # M<B   # L<B ! # K<B "@ # J<B # # I<B $ # H<B % # G<B &@ # F<B ' # E<2 ( # D<2 ) # C<2 * # B<2 + # Ar - 6@ r . 6 ?  r / 6 >  r 0 6 =  r 1 6 <  r 2 6 ;  r 3 6: r 4 69 r 5 68 r 6 67 r 7 66 r 8 65 r 9 64 r : 63 r ; 62 r < 61 r = 60 r > 6/ r ? 6. r @ 6- r A 6, <B B # +<B C@ # *<B D # )<B E # (<B F@ # '<B G@ # &B2 H 3 %~ I BI$ ~ J BJ# <B K@ # "<B L # !<B M #  <B N # <B O # <B P # <B Q # <B R # <B S # <B T # <B U # <B V # <B W # <B X # B2 Y 3 ~ Z BZ ~ [ B [  <B \@ # <B ] # <B ^ # @<B _ # @<B ` # @ <B a # @ <B b@ # @ <B c@ # @ H2 d C  <B e # @<B f # @<B g # @<B h # @<B i # @<B j # @H2 k C <B l@ # @<B m@ # @B S  ?  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghi6m  tl  tkr  tj w ti| }th  tg9 tfEtetdrtctbta|}t`t_# 2$ t^# $ t]#  t\ a t[A  tZQ  tYa # tXHtWh  tVgtU+5,tTv5wtS :tRTtQttPstO758tN5tMFtL#tKatJA(tIQ(tHa #tG& tF&q rtE tD 6 tC  tB E tA i P w t@% ?, t? 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