ࡱ> )+&'(q` 6bjbjqPqP  $::."""6z6S"˙˙˙$hE"4"˙44 4X8"4r " `#0SD(" ˙4nm;˙˙˙Դ˙˙˙S4444666H:MF666:M666  A Selected List of Resources on Verilog HDL & Xilinx FPGA Compiled By  Resource Centre Books available in Resource Centre Sr. No.TitlesArnold, Mark Gordon: Verilog digital computer design : algorithms into hardware New Jersey. Prentice Hall, 1999 621.392 ARN 017192Ashenden, Peter J. Digital design: an embedded systems approach using verilog Amsterdam. Elsevier, 2008 621.395 ASH 021341Bening, Lionel & Foster, Harry D. Principles of verifiable RTL design : a functional coding style supporting verification processes in verilog London. Kluwer Academic Publishers, 2000 621.392 BEN 002970Betz, Vaughn, Rose, Jonathan & Marquardt, Alexander Architecture and CAD for Deep-Submicron FPGAs London. Kluwer Academic Publishers, 1999 621.395 BET 002762Bhaskar, J. Verilog HDL Primer Hyderabad . BS Publications , 2001 621.382 BHA 004611Botros, Nazeih M. HDL programming fundamentals : VHDL and Verilog Hingham Da Vinci Engineering Press, 2007 621.392 BOT 016567Brown, Stephen & Vranesic, Zvonko Fundamentals of digital logic with verilog design New Delhi. Tata McGraw-Hill, 2003 621.392 BRO 004456Cavanagh, Joseph J. F. Digital design and Verilog HDL fundamentals Boca Raton. CRC Press, 2008 621.395 CAV 023019Cavanagh, Joseph VeriIog HDL : digital design and modeling Boca Raton. CRC Press/Taylor & Francis, 2007 621.392 CAV 015513Chonnad, Shivakumar S. & Balachander, Needamangalam B. Verilog : frequently asked questions : language, applications and extensions. (Springer International Edition) New Delhi. Springer, 2004 621.392 CHO 015592Ciletti, Michael D. Advanced digital design with the verilog HDL New Delhi. Prentice Hall of India, 2005 621.395 CIL 012569Ciletti, Michael D. Modeling, synthesis, and rapid prototyping with the verilog HDL New Jersey. Prentice Hall, 1999 621.392 CIL 006522- 006523Coffman, Ken Real world FPGA design with Verilog New Jersey. Prentice Hall PTR, 1999 621.395 COF 021880Deschamps, Jean-Pierre, Bioul, Gery Jean Antoine & Sutter, Gustavo D. Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems Hoboken. John Wiley & Sons, 2006 621.395 DES 017013Eccles, William J. Pragmatic logic San Rafael. Morgan & Claypool Publishers, 2007 621.395 ECC 020888FitzPatrick, Dan & Miller, Ira Analog behavioral modeling with the Verilog-A language Bolton. Kluwer Academic Publishers, 1998 621.381 FIT 020105Foster, Harry D., Krolnik, Adam C. & Lacey, David J. Assertion-based design Boston. Kluwer Academic, 2003 621.395 FOS 008625George, Varghese & Rabaey, Jan M. Low-Energy FPGAs - architecture and design London. Kluwer Academic Publishers, 2001 621.3815 GEO 002752Ghosh, Sumit Hardware description languages : concepts and principles New Delhi. Prentice Hall of India, 2001 621.392 GHO 005111Gokhale, Maya B. & Graham, Paul S. Reconfigurable computing : accelerating computation with field-programmable gate arrays New York. Springer, 2005 621.395 GOK 013923Kundert, Kenneth S. & Zinke, Olaf Designers guide to verilog AMS Boston. Kluwer Academic Publishers, 2004 621.392 KUN 012578Lee, James M. Verilog quickstart : a practical guide to simulation and synthesis in verilog London. Kluwer Academic Publishers, 1999 621.392 LEE 002969Lilja, David J. & Sapatnekar, Sachin S. Designing digital computer systems with Verilog Cambridge. Cambridge University Press, 2005 621.392 LIL 012819Maxfield, Clive Design warrior's guide to FPGAs : devices, tools, and flows New Delhi. Elsevier, 2004 621.395 MAX 014893Mazumder, Pinaki & Rudnick, Elizabeth M. Genetic algorithms for VLSI design, layout & test automation Delhi. Addison-Wesley, 1999 005.1 MAZ 000826Minns, Peter & Elliott, Ian D. FSM-based digital design using Verilog HDL Chichester. John Wiley & Sons, 2008 004.33 MIN 020404Mintz, Mike & Ekendahl, Robert Hardware verification with SystemVerilog : an object-oriented framework New York. Springer, 2007 621.392 MIN 019527Mittra, Swapnajit Principles of Verilog PLI London . Kluwer Academic Publishers , 2000 621.392 MIT 002974Murgai, Rajeev, Brayton, Robert K. & Sangiovanni-Vincentelli, Alberto Logic synthesis for field-programmable gate arrays London. Kluwer Academic Publishers, 1995 621.395 MUR 003047Navabi, Zainalabedin Embedded core design with FPGAs New York. McGraw-Hill, 2007 621.3815 NAV 016417Navabi, Zainalabedin Verilog digital system design: RT level synthesis, testbench and verification, 2nd ed. 621.392 NAV 021814Oldfield, John V. & Dorf, Richard C. Field-programmable gate arrays : reconfigurable logic for rapid prototyping and implementation of digital systems New York. WileyJohn Wiley & Sons, 1995 621.395 OLD 017507Padmanabhan, T. R. & Sundari, B.Bala Tripura Design through Verilog HDL New Jersey. IEEE Press, 2003 005.74 PAD 008572Palnitkar, Samir Verilog HDL : a guide to digital design and synthesis Delhi. Pearson Education Asia, 2001 621.382 PAL 002267-02269Ramachandran, Seetharaman Digital VLSI systems design : a design manual for implementation of projects on FPGAs and ASICs using verilog Dordrecht. Springer, 2007 621.395 RAM 016719Reese, Robert B. & Thornton, Mitchell Aaron Introduction to logic synthesis using Verilog HDL San Rafael. Morgan & Claypool Publishers, 2006 621.392 REE 020883Sagdeo, Vivek Complete verilog book London. Kluwer Academic Publishers, 2000 621.392 SAG 002973Sandige, Richard S. Digital design essentials New Jersey. Prentice Hall, 2003 621.381 SAN 007300Smith, David R. Verilog styles for synthesis of digital systems New Jersey . Prentice Hall , 2000 621.392 SMI 002744Smith, Michael John Sebastian Application-specific integrated circuits Delhi. Pearson Education Asia, 2001 621.382 SMI 000779Spear, Chris SystemVerilog for verification : a guide to learning the testbench language features New York. Springer, 2006 621.392 SPE 014692Stine, James E. Digital computer arithmetic datapath design using verilog HDL. Boston. Kluwer Academic Publishers, 2004 621.395 STI 013461Sutherland, Stuart Verilog PLI Handbook: users guide and comprehensive reference on the Verilog programming languages of a interface London. Kluswer Publishers, 1999 621.392 REF SUT 002971Sutherland, Stuart Verilog PLI handbook : a users guide and comprehensive reference on the Verilog programming language interface, 2nd ed. 621.392 SUT New Delhi. Springer, 2008 018477Sutherland, Stuart, Davidmann, Simon & Flake, Peter System Verilog for design, 2nd ed. New York. Springer, 2006 621.392 SUT 014694Sutherland, Stuart & Mills, Don Verilog and system Verilog gotchas: 101 common coding errors and how to avoid them New York. Springer, 2007 621.392 SUT 019539Sutherland, Stuart Verilog 2001 London. Kluwer Academic Press, 2002 621.3815 SUT 002748Thomas, Donald E. & Moorby, Philip R. Verilog hardware description language, 5th ed. New Delhi. Kluwer Academic Publishers, 2002 621.395 THO 017680Trimberger, Stephen M., ed. Field-programmable gate array technology. (Springer International Edition) New Delhi. Springer, 2007 621.395 TRI 015585 Wakerly, John F. Digital design: principles and practices, 3rd ed. New Delhi. Pearson Education Asia, 2001 621.382 WAK 010664- 010665Wolf, Wayne FPGA-based system design New Jersey. Prentice Hall, 2004 621.395 WOL 012573Zeidman, Bob Verilog designers library New Jersey. Prentice Hall, 1999 621.392 ZEI 002239Zeidman, Bob Designing with FPCAS and CPLDS Lawrence. CMP Books, 2002 621.395 2 ZEI 005497E BooksHandbook on Verilog HDL  HYPERLINK "http://www.ge.infn.it/~pratolo/verilog/Handboook_Bucknell.pdf" http://www.ge.infn.it/~pratolo/verilog/Handboook_Bucknell.pdfVerilog-A : Language Reference Manual - (Analog Extensions to Verilog HDL)  HYPERLINK "http://www.vhdl.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf" http://www.vhdl.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf CDs available in the Resource Centre Sr. No.Titles1Botros, Nazeih M. HDL programming fundamentals : VHDL and Verilog. Hingham. Da Vinci Engineering 621.392 BOT C013252Brown, Stephen & Vranesic, Zvonko Fundamentals of digital logic with verilog design. 621.392 BRO C004983Ciletti, Michael D. Advanced digital design with the verilog HDL. 621.395 CIL C00450, C00451 & C010214Ciletti, Michael D. Xilinx student edition 4.2i. (ISE student ed.) 621.392 CIL C006715Lee, James M. Verilog quickstart : a practical guide to simulation and synthesis in verilog. 621.392 LEE C004416Minns, Peter & Elliott, Ian D. FSM-based digital design using Verilog HDL. [Synapticad : verilogger extreme] 004.33 MIN C016257Navabi, Zainalabedin Verilog digital system design : RT level synthesis, testbench and verification, 2nd ed.. 621.392 NAV C016798Navabi, Zainalabedin Verilog Digital System Design. 621.392 NAV C006369Palnitkar, Samir Verilog HDL : a guide to digital design and synthesis. 621.382 PAL C00223 - C0023710Ramachandran, Seetharaman Digital VLSI systems design : a design manual for implementation of projects on FPGAs and ASICs using verilog. 621.395 RAM C0133311Sagdeo, Vivek Complete Verilog Book. 621.392 SAG C0044612Sandige, Richard S. Xilinx student edition 4.2i. 621.381 SAN C0071513Stine, James E. Digital computer arithmetic datapath design using verilog HDL. 621.395 STI C0111914Sutherland, Stuart Verilog PLI handbook : a user's guide and comprehensive reference on the Verilog programming language interface, 2nd ed.. 621.392 SUT C01449 C0144915Sutherland, Stuart Verilog PLI Handbook. [User`s Guide and Comprehensive Reference on the Verilog Programming Languages of a Interface] 621.392 REF SUT C0044516Thomas, Donald E. & Moorby, Philip R. Verilog hardware description language, 5th ed. 621.395 THO C0140217Thomas, Donald E. Verilog hardware description languages, 4th ed. 621.392 THO C0044018Zeidman, Bob Verilog Designer's Library. 621.392 ZEI C00437 Dissertations available in the Resource Centre Sr. No.Titles1Choudhary, Vivek Kumar FPGA implementation of direct sequence spread spectrum techniques Gandhinagar. Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT), 2008 621.38456 CHO T001792Rawat, Nitin FPGA implementation of image compression algorithm using wavelet transform Gandhinagar. Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT), 2008 621.3670151 RAW T00162Other resources Sr. No.Titles1Verilog-1995 - Quick Reference Guide  HYPERLINK "http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html" http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html Designer's Guide to VHDL, HARDWARE DESCRIPTION LANGUAGE (HDL)., FPGA (Field Programmable Gate Array)  HYPERLINK "http://www.doulos.com/" http://www.doulos.com/ A Verilog HDL Test Bench Primer : Application Note  HYPERLINK "http://www.latticesemi.com/lit/docs/appnotes/cpld/an013_1.pdf" http://www.latticesemi.com/lit/docs/appnotes/cpld/an013_1.pdf SystemVerilog - Video Gallery  HYPERLINK "http://www.doulos.com/knowhow/video_gallery/" http://www.doulos.com/knowhow/video_gallery/ Verilog Useful links http://www.asic-world.com/verilog/verilinks.html 2Proceedings: Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International  HYPERLINK "http://ieeexplore.ieee.org/xpl/RecentCon.jsp?punumber=3561" http://ieeexplore.ieee.org/xpl/RecentCon.jsp?punumber=3561 Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International  HYPERLINK "http://ieeexplore.ieee.org/xpl/RecentCon.jsp?punumber=5334" http://ieeexplore.ieee.org/xpl/RecentCon.jsp?punumber=5334   !#$%mXC.(hXhG5B*CJ OJQJaJ ph3f(hXhY_T5B*CJ OJQJaJ ph3f(h^,hI75B*CJ$OJQJaJ$ph3f(h^,h_@5B*CJ$OJQJaJ$ph3f(h^,hI5B*CJ$OJQJaJ$ph3f(hXhuv5B*CJ OJQJaJ ph3f(hXhI75B*CJ OJQJaJ ph3f(hXhd5B*CJ OJQJaJ ph3f(hXhI5B*CJ OJQJaJ ph3f(h^,h5B*CJ$OJQJaJ$ph3f  !%&24@ABKNPQSTUefgh$a$gd "gdG$a$gdY_T$ L^La$gd_@$a$gdI66%&.1234?@ABFGJԿԀkVA,A(hXhX5B*CJ OJQJaJ ph3f(hXhB^J5B*CJ OJQJaJ ph3f(h^,hhz5B*CJ$OJQJaJ$ph3f(h^,hI75B*CJ$OJQJaJ$ph3f(hXhy5B* CJ(OJQJaJ(ph(hXhG5B* CJ(OJQJaJ(ph(hXh_@5B* CJ(OJQJaJ(ph(hXhY_T5B* CJ(OJQJaJ(ph(hXhuv5B* CJ(OJQJaJ(ph,h^,h_@5B*CJ(OJQJ^JaJ(ph3f JKMNOQRSTUdefhijkzhVG5#h^,hqO5CJOJQJ^JaJh9\5CJOJQJ^JaJ#h^,h9\5CJOJQJ^JaJ#h^,hG5CJOJQJ^JaJ#h^,h=Z5CJOJQJ^JaJh^,hG5CJ0OJQJaJ0(jh^,h_@OJQJUmHnHuh^,h_@5CJ0OJQJaJ0(h^,h5B*CJ$OJQJaJ$ph3f(hXhB^J5B*CJ OJQJaJ ph3f(hXh_@5B*CJ OJQJaJ ph3fhijklmnpzkd$$Ifl0D%8 t0!644 la $$Ifa$gd$a$gd kmnotĭĖm]M]M>1h^,hzOJQJ^Jh^,hlCJOJQJaJh^,hl5CJOJQJaJh^,hF5CJOJQJaJ#h^,hqO5CJOJQJ^JaJ,hU3h(5B*CJOJQJ^JaJph,hU3hY_T5B*CJOJQJ^JaJph,hU3h{k5B*CJOJQJ^JaJph,hU3hB35B*CJOJQJ^JaJph#h^,h9\5CJOJQJ^JaJ#h^,hY_T5CJOJQJ^JaJ ' ( ) < kbbbb $Ifgdtzkdd$$Ifl0D%8 t0!644 la $Ifgdz$ & F$Ifa$gd- & ' ( ) ; < 4 5 p q r s    ɺ魜o`S`Dh^,hzDCJOJQJaJh^,h=%OJQJ^Jh^,h=%CJOJQJaJ h^,hjCJOJQJ^JaJh^,hjOJQJ^Jh^,hjCJOJQJaJ h^,h{/rCJOJQJ^JaJh^,h{/rOJQJ^Jh^,h{/rCJOJQJaJh^,hlCJOJQJaJ h^,hB^JCJOJQJ^JaJh^,hzOJQJ^Jh^,OJQJ^J 5 ^ j q tkkkkk $Ifgdt$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 laq r s  tkkkkk $Ifgdt$ & F$Ifa$gd-zkd,$$Ifl0D%8 t0!644 la   3 V b i tkkkkk $Ifgdt$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la  2 3 i j k | }  ? @ n o v w x Ȼ滱Ȣ敢yyyoy`h^,h *CJOJQJaJhqOOJQJ^Jh^,hK$OJQJ^Jh^,hK$CJOJQJaJh^,huOJQJ^Jh^,huCJOJQJaJh]{OJQJ^Jh^,hNOJQJ^Jh^,hNCJOJQJaJh^,hzDCJOJQJaJh^,hzOJQJ^Jh^,hzDOJQJ^J$i j k } tkkkkkk $Ifgdt$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la  @ b o v tkkkkk $Ifgdt$ & F$Ifa$gd-zkdX$$Ifl0D%8 t0!644 lav w x tkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la ( U b i tkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la ' ( a b i j k ?@ATUOPQ]^ȻȬ柬惐tgggth^,hqOJQJ^Jh^,hqCJOJQJaJh^,h9JOJQJ^Jh^,h9JCJOJQJaJh^,hjOJQJ^Jh^,hjCJOJQJaJh^,hk|OJQJ^Jh^,hk|CJOJQJaJh^,h *CJOJQJaJh^,hzOJQJ^Jh^,h *OJQJ^J&i j k ,8?tkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la?@AUtkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la4@Otkkkkk $IfgdzD$ & F$Ifa$gd-zkdL$$Ifl0D%8 t0!644 laOPQ^tkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 laDeqxtkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 laxyz67stu<ȻȻլtg]gtNh^,h@ CJOJQJaJh]{OJQJ^Jh^,hZOJQJ^Jh^,hZCJOJQJaJh^,hV0OJQJ^Jh^,hV0CJOJQJaJh^,hZW OJQJ^Jh^,hZW CJOJQJaJh^,hzOJQJ^Jh^,hRNOJQJ^Jh^,hRNCJOJQJaJh^,hCOJQJ^Jh^,hCCJOJQJaJxyztkkkkk $IfgdzD$ & F$Ifa$gd-zkdx$$Ifl0D%8 t0!644 la7`lstkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 lastutkkkkk $IfgdzD$ & F$Ifa$gd-zkd@$$Ifl0D%8 t0!644 laBktkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 latkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la-./<= Ȼ搃搝tgggtXKKh^,hjd_OJQJ^Jh^,hjd_CJOJQJaJh^,htOJQJ^Jh^,htCJOJQJaJh^,h')OJQJ^Jh^,hwMOJQJ^Jh^,hwMCJOJQJaJh^,hB3CJOJQJaJh hB3OJQJ^Jh hB3CJOJQJaJh^,h@ CJOJQJaJh^,hzOJQJ^Jh^,h@ OJQJ^J'tkkkkk $IfgdzD$ & F$Ifa$gd-zkdl$$Ifl0D%8 t0!644 la&-tkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la-./=tkkkkk $IfgdzD$ & F$Ifa$gd-zkd4$$Ifl0D%8 t0!644 la!MZatkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 la !YZabc#:CErst]^ȻȬylylyly]PlPlh^,h OJQJ^Jh^,h CJOJQJaJh^,hOJQJ^Jh^,hK$OJQJ^Jh^,hK$CJOJQJaJh]{OJQJ^Jh^,h*OJQJ^Jh^,h*CJOJQJaJh^,hOJQJ^Jh^,hCJOJQJaJh^,hjd_CJOJQJaJh^,hjd_OJQJ^Jh^,hzOJQJ^Jabcstkkkkk $IfgdzD$ & F$Ifa$gd-zkd$$Ifl0D%8 t0!644 laD`krtkkkkk $IfgdzD$ & F$Ifa$gd-zkd` $$Ifl0D%8 t0!644 larsttkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la^wtkkkkk $IfgdzD$ & F$Ifa$gd-zkd( $$Ifl0D%8 t0!644 la^@GTm./LȻȬwjw\h^,h H*OJQJ^Jh^,h8*OJQJ^Jh^,h8*CJOJQJaJh^,h]<CJOJQJaJh]{OJQJ^Jh]<h]<OJQJ^Jh]<h]<CJOJQJaJh^,hWOJQJ^Jh^,hWCJOJQJaJh^,h CJOJQJaJh^,hOJQJ^Jh^,h OJQJ^Jtkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la@stkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 latkkkkk $IfgdzD$ & F$Ifa$gd-zkdT $$Ifl0D%8 t0!644 la/tkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la3Zgntkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 lamnop01abhnopq '()ȻȟviiiivZh^,hCJOJQJaJh^,h')OJQJ^Jh^,h')CJOJQJaJh^,h9OJQJ^Jh^,htOJQJ^Jh^,htCJOJQJaJh^,hOJQJ^Jh^,h{/rOJQJ^Jh^,h{/rCJOJQJaJh^,hSGOJQJ^JhSGhSGOJQJ^Jh^,hSGCJOJQJaJ"noptkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la1Ubotkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 laopq 'tkkkkk $IfgdzD$ & F$Ifa$gd-zkdH $$Ifl0D%8 t0!644 la'()Utkkkkk $IfgdzD$ & F$Ifa$gd-zkd $$Ifl0D%8 t0!644 la)TU$%,-.  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