Introduction



Introduction

This book is not intended to be a novel or a text. It is a collection of informative reference material that is, otherwise, hard to come by. It is assumed that the reader has a working knowledge of electronics and basic digital logic. It is an introduction to TTL and the 74xxx family of logic devices. While it is not intended to cover CMOS devices, it does mention these as far as they over lap into the 74xxx part numbering system (74Cxxx, 74HCxxx, 74HCTxxx, 744xxx, etc).

In its best application, this literature would be part of a course so you have someone to help explain some of the things that are not so clear here in the text. It is not intended that this be a text book to read and learn everything there is to know about TTL. This book won't go into strong detail on basic concepts. It is an addition to a course that already covers basics.

Table of Contents Page

What is TTL? --------------------------------------------- 3 Internal Operation of TTL devices ------------------------ 4

Differences between 74xx, 74Lxx, 74LSxx, etc ------------- 5

Basic Logic ---------------------------------------------- 7

Edge triggers, level triggers, strobes, and enables ------ 9

Frequency Dividers --------------------------------------- 9

Drivers and buffers -------------------------------------- 10

Error Detection and Correction --------------------------- 11

Synchronous Counters and Ripple Counters ----------------- 12

Multiplexers and Demultiplexers, Encoders and Decoders --- 13

Decimal, Binary, Octal, Hexadecimal, and Bi-Quinary ------ 15

Ring Counters -------------------------------------------- 16

Shift Registers and UARTs -------------------------------- 17

FIFO Memories -------------------------------------------- 18

7400 Quad 2 input NAND gate ------------------------------ 19

7401 Quad 2 input NAND gate with Open Collector output --- 19

7402 Quad 2 input NOR gate ------------------------------- 19

7404 Hex Inverter ---------------------------------------- 19

7414 Schmitt Trigger, and Schmitt Triggers in general----- 20

7441 BCD to Decimal Decoder ------------------------------ 21

7442 BCD to Decimal Decoder ------------------------------ 21

7444 Excess-3 Grey to Decimal Decoder -------------------- 22

7445 BCD to Decimal Decoder ------------------------------ 22

7470 Single J-K Flip flop with AND Gated J and K inputs -- 23

7472 Single J-K Master - Slave flip flop ----------------- 23

7473 Dual J-K Master - Slave flip flop ------------------- 23

7474 Dual D-Type Flip flop ------------------------------- 23

7475 Quad D-Type Flip flop ------------------------------- 24

7476 Dual J-K Master - Slave flip flop ------------------- 24

7483 4 bit Binary Full Adder ----------------------------- 24

7485 Four bit comparator --------------------------------- 24

74107 Dual J-K Master - Slave flip flop ------------------ 25

74120 Dual Pulse Synchronizer ---------------------------- 25

74121 Retriggerable Monostable Multivibrator ------------- 25

74145 BCD to Decimal Decoder ----------------------------- 26

74180 8 bit odd and even parity generator and checker ---- 26

74181 Arithmetic and Logic Unit (ALU) -------------------- 27

74184 Bi-Quinary to Binary converter --------------------- 29

74185 Binary to B-Quinary converter ---------------------- 30

74259 8 bit Addressable Latch ---------------------------- 31

74279 Quad S-R Latch ------------------------------------- 31

What to do with unused inputs, and why. ------------------ A

Why you can't tie Totem-Pole outputs together. ----------- B

Note on CMOS part numbers in the 74xxx series. ----------- C

Power Supply requirements for TTL. ----------------------- D

Glossary. ------------------------------------------------ E

Numerical Listing of 74xxx part numbers ------------------ F

What is TTL?

(ref. NAND.SCH)

TTL stands for Transistor - Transistor Logic. Inputs of the gates go directly into a transistors emitter. This is in contrast to DTL (Diode - Transistor Logic) that had diodes do the ANDing function, or the older RTL (Resistor - Transistor Logic) where the resistors did the ANDing function. TTL has input transistor that have multiple Emitters (for a AND or NAND gate) each of which is an input. This is functionally equivalent to DTL, but the major change is the manufacturing process.

In the early years of TTL, various families of TTLs evolved, each identifiable by a different series of numbers (9xxx series, 74xxx series, etc). The most standard and popular of these became the 74xxx series. The 74xxx TTL family has evolved over the years to create lower power, and / or higher speed. Sometimes these changes were as minor as changing resistor values. In 74Lxxx devices the values of the resistors were increased. These devices drew less current than their 74xxx counterparts, but had the disadvantage of being slower. 74Hxxx devices had smaller internal resistances making them faster than their 74xxx brothers. The disadvantages of this was a marked increase of current (and therefore an increase in heat, which proved to be a major flaw).

The next major development of the 74xxx series was the use of Schottky transistors. The speed of 74xxx devices was built into the structure of the transistor itself. A reverse biased diode (or transistor junction) has an inherent capacitance. This capacitance, and the inherent internal resistances of the circuit, limited the upper frequency range of the devices. By using Schottky diodes and transistors (with lower capacitances) higher speeds were allowed without the cost of higher currents, or that evil demon, heat. These devices are noted by an S in the part number. 74Sxxx devices have speeds in the range of the old 74Hxxx devices. 74LSxxx devices gave the speed of 74xxx with the lower current of 74Lxxx.

The most recent change in technology came when we could drastically reduce the size of the transistor. 74Axxx devices (Advanced technology) have architectures one tenth the size of their predecessors. The smaller transistor meant a smaller gate which put the gates closer together, thus faster. All advances have a cost. The cost of 74Axxx devices is the small, thinner, more delicate transistor is more sensitive to static electricity, and need to be handled as though they were CMOS devices. The 74Axxx technology was combined with others to make 74ASxxx, 74ALSxxx, etc.

The fastest, and newest of the bipolar technology is the 74ASxxx. Various manufactures alter this part number system to some degree. Some call it 74Fxxx (Fast), or 74FASTxxx. These are still a variation of the 74ASxxx system.

The standardization of 74 series numbers has ever entered into CMOS devices. There are devices labelled 74Cxxx, 74HCxxx, 74HCTxxx, 74FACTxxx, 74ACxxx, or 744xxx. These are CMOS devices (but, that's another book).

Internal Operation

(ref. DEM7400.SCH)

Page DEM7400.SCH text describes how the internal operation of TTL gates works.

Current flow between gates.

(ref. DEM7400.SCH)

Page DEM7400.SCH text describes how current flows between gates. For the most part, this need not be considered when analyzing TTL circuits. What counts is data flow, not current flow. It's nice to know, but not necessary.

Differences between 74xx, 74Lxx, 74LSxx, etc

(ref. NAND.SCH for RA)

Input characteristics for various types.

Family RA IH IL

74xx 4K 40 uA -1.6 mA

74ALSxx 40K 20 uA -0.1 mA

74ASxx 8K 20 uA -0.5 mA

74Hxx 2.8K 50 uA -2.0 mA

74Lxx 40K 10 uA -0.18 mA

74LSxx 18K 20 uA -0.4 mA

74Sxx 2.8K 50 uA -2.0 mA

RA of NAND.SCH is just used as an example of how much the values change. All values are adjusted by about the same amount. The circuit shown is a simplification of a NAND gate. Real circuits will vary notable. For instance, the resistors are not carbon type resistors, they are transistors biased into conduction just enough to give an effective resistance. Likewise, the diodes are Emitter Base junctions of transistors with the Base and Collector tied together. The area between Q2 and Q3 and Q4 often has more circuitry to speed up a High output, or limit the current of Q3 and Q4. Tri-State drivers have a circuit in this area to turn off both Q3 and Q4 when it is Tri-Stated.

Output characteristics for various types.

Family OH OL

74xx 400 uA -16 mA

74ALSxx 200 uA -1.0 mA

74ASxx 200 uA -5.0 mA

74Hxx 500 uA -20 mA

74Lxx 100 uA -1.8 mA

74LSxx 200 uA -4.0 mA

74Sxx 500 uA -20 mA

Buffers typically drive four times the above values.

Fanout and drive capability between families

drive driven

74xx 74ALS 74ASxx 74Hxx 74LSxx 74Sxx

74xx 10 80 80 8 40 8

74ALSxx 5 40 40 4 20 4

74ASxx 12 100 100 10 50 10

74Hxx 12 100 100 10 50 10

74LSxx 5 40 40 4 20 4

74Sxx 12 100 100 10 50 10

74Lxx 5 40 40 4 20 4

Speed (clock frequency for a simple gate)

Family

74xx 35 MHz

74ALSxx 50 MHz

74ASxx 175 MHz

74Hxx 50 MHz

74Lxx 3 MHz

74LSxx 45 MHz

74Sxx 125 MHz

Basic Logic

(ref. GATES001.SCH)

Logic gates mimic the human thought process. The basic gates are the AND, OR, Exclusive-OR, Latch, Inverter, and Buffer. The AND requires that in order to get the desired output, all inputs must be active. The OR gate requires that any input may be active in order to get the desired output. The Invertor does exactly what its name implies, it inverts a 1 to 0, or 0 to 1. The Non-Inverting Buffer does not invert. (The connotation of "Buffer" varies from manufacturer to manufacturer, or even era to era. This will be covered more later.)

The shape of the body gives indication of the logic process involved. There is a distinctive AND function, and a distinctive OR function. Plain lines for input and outputs indicate active Highs. A Dot on the input or output indicates an Active Low.

The basic gates may be used in combination to create other basic gates. A two input AND gate requires that both inputs must be High to get a High out. If we desire to have a Low out under those conditions, we put an invertor on the output of the AND. We have an Inverting AND or NAND. Likewise, an Inverting OR is a NOR. We also have an Inverting Exclusive-OR called Exclusive-NOR.

The Exclusive-OR is a modification of the OR gate. In order to get the desired output any input may be active, but not all of them. These have application in comparing two values, or performing binary addition. The table below shows what the inputs and outputs are for a two input Ex-OR.

A B Out

0 0 0

1 0 1

0 1 1

1 1 0

Any 1 in gives a 1 out, but not both. This performs a binary Half-Add. 1 plus 0 equals 1. 0 plus 1 equals 1. 0 plus 0 equals 0. 1 plus 1 equals 0, plus a Carry. The lack of consideration for Carry makes this a Half-Adder. If we add circuitry to an Ex-OR to allow for a Carry In to this stage, and Carry Out from this stage we have a Full Adder.

The Latch is the basic memory cell. It records that an event happened. The basic latch is the SR Latch. It has a Set input and a Reset input. This is demonstrated on sheet GATES001.SCH which shows an Active Low SR latch.

In the Reset state (Reset input Low, Set input High) the Q Output is Low, and the Q-bar output is High. Once in the Reset state the input may now be removed and the latch will stay Reset. To Set the latch bring the Set input (S) low. Q goes High, and

Q-bar goes Low. The latch is now set. The set input may be removed and the latch will stay in the Set state (until Reset). If both Set and Reset inputs are applied at the same time, the latch "Jams". In TTL technology logic, both outputs will go High. (In CMOS technology logic, both outputs go Low.) Which ever input goes away first looses, and the latch assumes the opposite state.

Complex functions may be configured using multiple gates. Multi-stage comparators, Adders, registers, and so on. At present about the hottest thing on the market is the 80586 (Pentium) used in the newer IBM PC compatibles. It has the equivalent of about four million gates.

Edge triggers, level triggers, strobes, and enables

An edge triggered latch is one that acts on the rising (leading) edge, or the falling (trailing) edge of a pulse. What ever the data input is at the time of the transition is what the latch gets set to. On level triggered latches the output will follow the input as long as the clock is at its active level. When the clock goes away, the latch stays in what ever state it was last in.

Both require a certain set-up time that the data must be stable before the clock latches the data. See Setup Time.

A strobe input usually indicates there is not latching function involved with this signal. It is an enable signal that effects the output of a gate. The term Enable usually refers to an input function that is being effected. These terms are not universally accepted, but popular used with this definition. In simpler gates, either term is used (like Tri-state drivers). Generally, outputs are Strobed, inputs are Enabled. Memory devices tend to use Enable for either inputs or outputs.

Frequency Dividers

A circuit that takes an input clock and counts the pulses, thereby dividing the input signal by some value. Usually the final output has a 50% duty cycle. Intermediate outputs may, or may not have any significant pattern to them.

A Frequency Divider designed for a Frequency Synthesizer is likely to have all outputs with a 50% duty cycle. Whereas, a Frequency Divider for a microcomputer timing circuit is more likely to have a binary or decimal weighted output code.

Drivers and buffers

These terms have overlapping definitions. In general, a Buffer has a higher drive current capability than normal gates, by a factor of four. Instead of a fanout of ten, they have a fanout of forty. The term Buffer is also used to describe a non-inverting gate that isolates two circuits while still allowing signal transfer. Like a Buffer stage is used between oscillators and the circuits they drive. This prevents the driven circuits from loading down the oscillator. Address Buffers are used between the CPU and the Address Bus to keep the Address Bus from loading down the CPU, usually only capable of driving a milli-Amp or so. Same for Data Bus Buffers.

Driver is a term usually used to identify output circuits that drive high current loads (50 mA to hundreds of mA, or more). However, some manufacturers refer to Bus Drivers, and Clock Drivers. The terms do not have universally accepted definitions, and can be easy to confuse. In either case the term refers to something with higher than normal drive current capability, and/or breakdown voltage of the output transistor.

Error Detection and Correction

Parity schemes (see 74180) are good for detecting that an error has occurred, but that is all they can do, detect an error. The next step up in progress would be a system that detects which bit is in error and invert it back to its normal state.

In a 16 bit system this is done by doing multiple parity checks on specific sections of the word. One parity bit checks bits 0, 1, 4, 5, 8, 9, 12, and 13. A second bit checks bits 2, 3, 6, 7, 10, 11, 14, and 15. Another bits, 0, 3, 6, 9, and 12. A forth bits 1, 4, 7, 10, and 13. A fifth bits, 2, 5, 8, 11, 14. And a sixth checks bits 3, 6, 9, 12, and 15. The six extra bits are stored in memory along with the 16 bits of data. When the data is read from memory and a parity error occurs, we can deduce which bit is in error by looking at what sections of the word came up with the wrong parity. Each bit position, if it were in error, would result in a predictable pattern when doing a parity check. This resulting pattern is called a Syndrome. A specific Syndrome code would result if, say, bit 4 were the one suspected as bad. All we have to do to correct the error is invert bit 4 as the word is read from memory.

All this extra operation costs us a little in the way of time, usually about 50 nano-seconds. Not a bad price for adding the capability. Most EDC systems are very capable of detecting and correcting single bit errors, and most can detect if more than one bit were in error (the Syndrome code was not one that indicated a single bit error). Typical EDC systems correct single bit errors and "flag" double bit errors. That is, they indicate to the CPU that an uncorrectable parity error has been encountered.

The pattern described above is typical of the method, but not the only pattern available.

Synchronous Counters and Ripple Counters.

The 7493 is a good example of a Ripple Counter. A lower stage toggling goes to the clock of the next higher stage and toggles it, which toggles the next higher stage, which toggles the next higher stage. After each clock pulse there is a period of chaos before the latches settle. This can be as long as 50 nano-seconds. This period of chaos can cause an erroneous effect on a decoder interpreting the output. For that 50 ns the outputs of the decoder glitch randomly. This also limits how high a frequency the counter can operate. As we get to higher clock speeds there becomes less difference between the width of the clock pulse and the glitches in our outputs.

Synchronous counters are an improvement on this design. The 74193 is a good example of such a counter. The outputs of the counters are feed back to the data inputs. On the clock, all outputs change at the same time, according to the state of the last outputs. The counter goes from stable state to stable state with none of the chaos associated with Ripple Counters.

This also makes for an easy design to count upwards or backwards, or shift up or down.

(ref. DEM7490.SCH, DEM7491.SCH, DEM7492.SCH, DEM7493.SCH)

These are a series of Ripple counters. The 7490 is a Divide by 10 (2 and 5), the 7491 is an eight stage Shift Register (only serial in and serial out available), the 7492 is a Divide by 12 (2, 3, 2), and the 7493 is a straight four bit Binary Counter.

On the 7490, 7492, and 7493 there are two sections. One is a Divide by 2, and the second section divides by 5 (7490), 6 (7492), or 8 (7493). The second section of the 7492 is actually a Divide by 3 followed by a Divide by 2 to make the output symmetrical.

Multiplexers and Demultiplexers, Encoders and Decoders

(ref MUXDEMUX.SCH)

A Multiplexer is a device that has many inputs, and selects one of those to be at the output.

The 74151 has 8 data inputs (D0 - D7), three select inputs (A, B, C), and an enable, G. It has a one bit output, Y, and its complement, W. The value on the select inputs specifies which of the eight inputs will be forwarded to the output.

The 74153 has two sets of four inputs (1C0 - 1C3, and 2C0 - 2C3), two select bits, A and B, and two enables (1G, and 2G). The select code specifies which of the inputs will show up at the output. A 00 selects both 1C0 to show up at 1Y, and 2C0 to show up at 2Y.

The 74157 has two sets of four inputs, 1A - 4A, one select input, Anot/B, and one enable. If Anot/B is Low the A inputs show up at the outputs. If Anot/B is High, the B inputs show up at the outputs.

The 74154 is a basic four to sixteen decoder. A four bit binary value on the input sets one of the outputs low that is equal to the input code. The 74LS138 is a basic three to eight decoder. A three bit binary code on the input selects one of the outputs to be low (as long as the Enable inputs G1, G2A, and G2B are activated).

The circuit in Figure 1 shows a general idea of how to pass eights bits of data over three wires. (Please bear in mind that this is not a flawless design, and is intended for the purpose of showing a multiplexing scheme.) Data is loaded into the latch (U1). The same clock that loaded U1 also cleared counter U2, U4, and U5, at the other end of the line. At the time of the load the counter U2 is at 000, selecting bit zero through U3. Counter U4 is also at 000. If D0 were a 1, bit one would end up set in U5 output.

(( A word about U5, 74259. This is an addressable latch, a register of eight latches which can be set or reset one at a time. The 74259 has three select inputs (S0, S1, and S2) to indicate which bit position is being referenced, a Data input to say to which state that latch is to be set, and a G input which is an Enable.

To set latch 2, put an input code of 010, set the Data input High, and enable the G input.

The Clear input is asynchronous (does not have to be accompanied with the G enable), and clears all eight latches.))

As the counter U2 and U4 count, the same clock pulses that increment the counter, select which input is going to be transmitted down the line. As they are received at the other end, they accumulate in U5 output.

A more unique circuit, but truly functional, is that of Figure 2. This is how to get eight Interrupt request lines into a CPU that has only one Interrupt request line. (The processor is an 8080. When the 8080 recognizes an Interrupt Request, it sets the Interrupt Acknowledge line low. During this time the interrupting device can set an instruction on the data lines for the processor to execute (one instruction). An ideal instruction for this is one of the Restart Instructions (C7, CF, D7, DF, E7, EF, F7, or FF). Each of these starts the processor executing at specific address (00, 08, 10, 18, 20, 28, 30, or 38). This arrangement makes for a convenient way to enter interrupt service routines.

The 74148 is a Priority Encoder. It has eight interrupt inputs, an Enable Input, Enable Output, a three bit output code (A0 - A2), and a GS output. The A0 - A2 outputs reflect a code that is equal to the highest valued active input. The GS output goes low anytime any of the inputs go low. Enable Input and Enable Output are for cascading more than one 74148 together. If Interrupts occur on Request lines 2, 4, and 6, the GS output goes low giving an Interrupt Request to the CPU. Since 6 is the highest ordered line, the A0 - A2 output will have a 6 on them.

This 6 goes to the 74ALS2450 input at bits 4, 5, and 6. When the 74ALS2450 is read at Interrupt Acknowledge time what gets dumped on the bus is our Restart code, whose specifics are dictated by what the Interrupt Request line was. (Honest, this really works!)

Decimal, Binary, Octal, Hexadecimal, and Bi-Quinary

Decimal (base 10) is what we think of as a normal number system. Each digit position has ten possible numbers (0 to 9), and each digit position to the left is ten times more than the one on its right. We have 1's, 10's, 100's, 1000's, etc.

Octal (base 8) is a system that has only eight possible numbers (0 to 7), and each digit position to the left is eight times more than the one to its right. We have 1's, 8's, 64's, 512's, etc.

Binary (base 2) is a system that has only two possible numbers, 0 and 1. A digit is either a one (High), or zero (Low). Each digit position to the left is two times more than the one on its right. We have 1's, 2's, 4's, 8's, etc. This is easiest to implement into circuitry because a latch has two possible states.

Hexadecimal (base 16) is a system that has sixteen possible numbers. Being limited to a language that only recognizes ten numbers, we improvise by continuing after nine by starting with the alphabet (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F). Each digit to the left 1s 16 times more than the one on its right. We have 1's, 16's, 256's, 4096's, etc.

The Bi-Quinary system requires a little more explaining. As the name implies, it is a 2 and 5 number system. That is, a bi-quinary counter divides by 2, then divides by five before it carries to the next position. Each bi-quinary digit is a digit-pair of two numbers. One counts from 0 to 4 (5 states), the next counts from 0 to 1 (2 states). A bi-quinary count goes like this.

0 000 0

0 001 1

0 010 2

0 011 3

0 100 4

1 000 5

1 001 6

1 010 7

1 011 8

1 100 9

To continue beyond one digit pair ...

0 000 0 000 0

0 000 0 001 1

0 000 0 010 2

0 000 0 011 3

0 000 0 100 4

0 000 1 000 5

0 000 1 001 6

0 000 1 010 7

0 000 1 011 8

0 000 1 100 9

0 001 0 000 10

0 001 0 001 11

0 001 0 010 12

0 001 0 011 13

0 001 0 100 14

0 001 1 000 15

0 001 1 001 16

0 001 1 010 17

0 001 1 011 18

0 001 1 100 19

0 010 0 000 20

Other counting methods are possible, but have limited application. For an example see the 7444, a Excess-3 Grey code Decoder.

Ring Counters

A typical Ring counter is a series of latches in which only one bit is set at a time. When it gets a clock, that latch clears and the next latch in the string sets. When it gets to the end of the string, it starts all over again at the lower bit.

Shift Registers and UARTs.

The Shift Register has similarities to the ring counter, but data may be entered into it. Data is entered at one end of the string of registers, and on each clock pulse the data shifts up the string one position.

Some shift registers are capable of shifting data in both directions. Least significant bit positions to higher bit positions (up shift, or right shift), or high to lower (down shift, or left shift). (Left and right is conventional, assuming data flows from left to right across the page.)

Some shift registers may be loaded in parallel (all bits loaded at once), or read from in parallel. These can convert serial data streams to, and from, parallel data streams. A UART1 is usually a pair of shift registers. One register converts parallel data from the processor to serial data as it shifts it out. The other register converts serial data coming in to parallel data for the processor to read.

1 A UART is a Universal Asynchronous Receiver and Transmitter. These are the devices used in digital communications. Asynchronous implies that only the data is sent. The bit rate is fixed frequency at both ends.

This is in contrast to a SRT (Synchronous Receiver and Transmitter) that supplies a clock for every bit position being transmitted. These clocks shift the shift register as data comes in. SRT designs are faster and more reliable, especially when there is motion, or long distances, between stations. UART designs are cheaper, and adequate for most applications.

FIFO Memories

FIFO is an acronym for First In First Out. Is usually a small array of registers that make up a memory. No addressing is required. Data is strobed into the inputs, stored as needed, and read from the output in the same order as it came in. These are typically used as an interface (or bridge) between two circuits, each working at their own speed. Instead of trying to synchronize communication between the two circuits, a FIFO is used. One circuit can stuff data into the FIFO as required. The other circuit takes from the FIFO at it's leisure. Usually flags indicate to each side of the circuit that the FIFO is empty, or has data for to be read.

A "16 by 4 FIFO" has 4 bit wide data, and is 16 registers deep. As data is strobed into the input it is automatically stored into location 0, 1, 2, 3, etc. As data is read from the FIFO, it is automatically read from location 0, 1, 2, 3, ... All addressing is handled internal to the FIFO.

On the Input side of the FIFO, a flag indicates to the circuitry that memory is available (or that the FIFO is empty). When the processor sees this flag, it sends data to the FIFO.

On the Output side of the FIFO, a flag indicates to the circuitry that there is data in FIFO to be read (or that FIFO is full). When the processor on that side sees the flag, it reads data from the FIFO until the flag is cleared (indicating the FIFO is empty).

7400 Quad 2 input NAND gate.

(ref. DEM7400.SCH)

DEM7400.SCH shows the basic internal structure of the 7400, and how it works. This is the basic Totem-Pole output, and basic TTL input. Schottky and Advanced devices are more complex in order to reach higher speeds, and protect inputs against static electricity.

7401 Quad 2 input NAND gate with Open Collector output.

(ref. DEM7401.SCH)

DEM7401.SCH shows the basic internal structure of the 7401 and how it works. Figure 1 and Figure 2 show a comparison between the Totem-Pole and the Open Collector structures. Figure 3 shows how the input would have been in DTL devices. There is no functional difference between 2a and 2b. The three diodes that make up the AND gate are similar in function to the two emittered NPN transistor. The difference is only in the manufacturing process of making up the transistor.

All open collector devices require an output load of some kind to pull it up to VCC. This may be just a resistor, or some functional load (Id Est; an LED, a relay, or such). The open collector configuration also allows multiple outputs to be tied together.

7402 Quad 2 input NOR gate.

(ref. DEM7402.SCH)

The circuitry on the left is a representation of the 7402. As can be seen, the inputs are into a single emittered transistor, and the ORing is done at Q3 and Q4. The output is a standard Totem-Pole arrangement.

7404 Hex Inverter

7414 Schmitt Trigger

(ref. DEM7414.SCH)

The internal workings of a 7414 can be seen in DEM7414.SCH, figure 1. The previous paragraph about Schmitt Triggers applies to the 7414, and other gates.

DEM7414.SCH shows the versatility of Schmitt Triggers. Figures 2 and 3 show basic oscillator circuits. Figure 3 shows how to use a transistor to amplify the capacitance of C1. Using this circuit a smaller value of C1 is possible. The effective capacitance is about equal to C1 times the DC gain of the transistor.

Figure 4 shows a basic Power On Reset circuit that gives a good square wave out. The diode gives the capacitor a quick discharge path when power is turned off.

Figure 5 shows how to use a Schmitt Trigger directly from an AC signal. This is not a suggested method, but will work. The internal diodes of the Schmitt Trigger protect the gate if power should rise above VCC, or go below 0 V. The resistor limits the current to values in a safe region for these diodes, and should be adjusted, as necessary. Figure 6 shows an improved version, and Figure 7 shows a suggested method.

Schmitt Triggers are also used on data and address buses to square up wave shapes that tend to get corrupt as they run along long bus lines.

On normal inputs, a valid Low In is anything below about 0.3 Volts, and a valid High In is anything about 3.5 Volts. Anything in between these levels is vague. A good square wave only stays here for nano-seconds, so this isn't usually a problem. But not all signals on a board are this clean.

Input signals from off the board can a well rounded leading edge (low frequency loss), or a erratic wave form that isn't a good square wave. A Schmitt trigger is designed to narrow this range of uncertainty. The input is designed to see anything below 0.9 volts as a low. Anything above 1.6 Volts is a High. This window between 0.9 Volts and 1.7 Volts has a hysteresis characteristic. When the signal is going high, it isn't called a valid high until it reaches 1.7 Volts. It won't be called a low until it goes down below 0.9 Volts.

These have good application for cleaning up inputs from switches, oscillators, RC timing circuits, or taking 60 Hz and outputing a nice clean square wave.

For other Schmitt Triggers see:

7413 Dual 4 input NAND Schmitt Trigger.

7418 Dual 4 input NAND Schmitt Trigger.

74132 Dual 4 input NAND Schmitt Trigger.

74242, 74243 and many other Bus Drivers are also Schmitt Trigger devices.

7431 Hex Delay Line

(ref.DEM7431.SCH)

This IC consists of two Inverters which delay 27 ns, two Buffers which delay 46 ns, and Two NAND gates which delay 6 ns.

7441 BCD to Decimal Decoder.

(ref. LATCHES1.SCH)

Active low outputs, open collector, 70 V, 7 mA.

Designed to drive gas filled tubes (neon). These are the orange, non-7 segment type displays popularly called "Nixie" tubes. The tube has the shape of a small radio tube, and has 10 wire screen cathodes, each in the shape of a number 0 through 9. There is a common anode that connects to high voltage (90 VDC) through a current limiting resistor. Output voltage, when low, is typically 1.4 VDC to 2.5 VDC. Typical output current is about 1 mA. Most of the time the tube was built to be viewed from the side, but some designs were made to be viewed from the top.

A BCD code on the input selects one of the outputs to be active (low), which turns on that number.

Note the odd power pins, VCC is pin 5, Gnd is pin 12.

7442 BCD to Decimal Decoder.

Active low out, normal Totem-pole output.

A BCD code on the input selects one of the outputs to be active (low). Outputs are designed to drive normal logic gates, etc.

7444 Excess-3 Grey to Decimal Decoder.

Grey code is a code that has no more than one bit changing as the count progresses. Excess-3 Grey is a modified Grey code that starts at a Grey code 3 (0010) and progresses, again, changing no more than one bit at a time. A 7444 is a Excess-3 Grey code decode, 7443 is Excess-3 decoder. Both of these only decode the first 10 (0 to 9) codes.

Typical application of these were to decode the position of a wheel. A pattern on the wheel contained the Grey code of progression. If a proper binary pattern were used, having more than one bit changing at a time would cause ambiguity when the wheel is changing counts. In Grey codes, only one bit position is changing at a time, giving a count with less ambiguity.

You might note that in Excess-3 Grey the code from 0 (0010) to 9 (1010) may be cycled through fully, without changing more than one bit at a time.

Grey code Excess-3 Grey (7444)

IN OUT IN OUT

DCBA DCBA

0000 0 0010 0 (3 in Grey code)

0001 1 0110 1

0011 2 0111 2

0010 3 0101 3

0110 4 0100 4

0111 5 1100 5

0101 6 1101 6

0100 7 1111 7

1100 8 1110 8

1101 9 1010 9

1111 A 1011 A

1110 B 1001 B

1010 C 1000 C

1011 D 0000 D

1001 E 0001 E

1000 F 0011 F

7445 BCD to Decimal Decoder.

Active low out, OC, 30 VDC, 80 mA.

A BCD code on the input selects one of the outputs to be active (low).

7470 Single J-K Flip flop with AND Gated J and K inputs.

Active low Preset and Clear inputs can only function when the clock input is low (inactive). J (and K) inputs have one active low and two active high inputs ANDed together. The clock input is Positive Edge triggered.

When the clock input goes high the latch will set if all J inputs are enabled, or clear if all K inputs are enabled. If neither J or K inputs are fully enabled, the output will not change from its current state. If both J and K inputs are enabled, the output will toggle states (if Set, it will clear. If Clear, it will Set). Once the clock returns low the Preset and Clear inputs may be used to change the state of the flip flop.

7472 Single J-K Master - Slave flip flop.

Active low Preset and Clear. J (and K) has a three inputs that are ANDed together. Both the J and K AND gates have a fourth input that is tied to the clock input.

The Master - Slave configuration means that there are functionally two flip flops. The Master flip flop follows the J and K inputs when the clock goes high. When the clock goes low the inputs of the Master flip flop is locked out, and the Slave flip flop will follow the what ever state the Master flip flop was last in. The output is the output of the Slave flip flop. The clock input is negative edge triggered, but you should keep in mind that the output will not be updated until the clock returns high. This is sometimes called a Delayed Output.

7473 Dual J-K Master - Slave flip flop.

Active low Clear with no Preset. J and K are single inputs. The Master - Slave configuration means that there are functionally two flip flops. The Master flip flop follows the J and K inputs when the clock goes high. When the clock goes low the inputs of the Master flip flop is locked out, and the Slave flip flop will follow the what ever state the Master flip flop was last in. The output is the output of the Slave flip flop. The clock input is negative edge triggered, but you should keep in mind that the output will not be updated until the clock returns high. This is sometimes called a Delayed Output.

Note the odd power pins, VCC is pin 4, Gnd is pin 11.

7474 Dual D-Type Flip flop.

When the Clock input goes high, the Q output follows the state of the D input. Q not is always the opposite of Q (unless the latch is jammed). Preset and Clear are active low inputs that override the clock function. If both Preset and Clear are active at the same time the output Jams. TTL devices will jam with both outputs high. CMOS devices will jam with both outputs low.

7475 Quad D-Type Flip flop.

This circuit is made of two sets of two D-Type Flip flops. Each set has its own clock input. It may be used as two sets of two, or the clocks may be tied together to make a four bit latch. Both Q and Q not outputs are available. (See the data sheet for typical applications.)

Note the odd power pins, VCC is pin 5, Gnd is pin 12.

7476 Dual J-K Master - Slave flip flop.

Active low Clear and Preset. J and K are single inputs. The Master - Slave configuration means that there are functionally two flip flops. The Master flip flop follows the J and K inputs when the clock goes high. When the clock goes low the inputs of the Master flip flop is locked out, and the Slave flip flop will follow the what ever state the Master flip flop was last in. The output is the output of the Slave flip flop. The clock input is negative edge triggered, but you should keep in mind that the output will not be updated until the clock returns high. This is sometimes called a Delayed Output.

Note the odd power pins, VCC is pin 5, Gnd is pin 13.

7483 4 bit Binary Full Adder

This IC has two sets of four inputs, A and B. and a Carry In. The output is a four bit sum, and a Carry Out. It does only one operation, adds A and B inputs. It is made to be cascadable to make Adders wider than 4 bits. Typical application would be in Memory Mapping schemes in Minicomputers, where a 16 bit value in a program is Added to an 8 bit value in memory control (representing bits A12 through A19), resulting in a memory address that is 20 bits long (1 MB memory). [For those who wonder how we can get megabytes of memory in a 16 bit machine, the answer is Memory Mapping.]

Note the odd power pins, VCC is pin 5, Gnd is pin 12.

DEM7483.SCH shows an example of Adding two 8 bit values together. Note that this is a Full Adder, that takes care of Carries between stages.

7485 Four bit comparator.

The 7485 has two sets of four bit inputs (A0 -A3, B0 - B3). It compares these two inputs and comes up with a three bit evaluation code. AB (A is greater than B), and A=B (A equals B). These outputs may be fed into the inputs of another 7485 (cascaded) for comparing more than four bits.

DEM7485.SCH is an example of a scheme to compare two 8 bit values. U1 compares the lower four bits, its evaluation code inputs are hard wired to give an A=B indication. U2 compares the upper four bits. The evaluation code outputs of U1 are fed to U2 evaluation code inputs. The evaluation code outputs of U2 give an overall indication of the two 8 bit values.

74107 Dual J-K Master - Slave flip flop.

Active low Clear with no Preset. J and K are single inputs. The Master - Slave configuration means that there are functionally two flip flops. The Master flip flop follows the J and K inputs when the clock goes high. When the clock goes low the inputs of the Master flip flop is locked out, and the Slave flip flop will follow the what ever state the Master flip flop was last in. The output is the output of the Slave flip flop. The clock input is negative edge triggered, but you should keep in mind that the output will not be updated until the clock returns high. This is sometimes called a Delayed Output.

This is an improved 7473 with conventional power pins.

74120 Dual Pulse Synchronizer

(ref. DEM74120.SCH)

Designed to synchronize an asynchronous (manual) signal with a stream of clock pulses and assure full pulse width of all pulses. Reset stops the pulse stream. Set starts the pulse stream.

The Mode input controls whether the output will be a stream of pulses (as mentioned above), or just one pulse. If mode is High the output will pass only one pulse after Set goes Low, and automatically stop. To get another pulse out the 74120 must be Reset and Set again. If the Mode input is low, the output will a stream of pulse.

74121 Monostable Multivibrator

(ref DEM74121.SCH)

The 74121 is a Monostable Multivibrator with two active low ORed enables, and a Schmitt Trigger input ANDed to the two low inputs. A monostable multivibrator is a latch that has only one stable state, Reset. It can be set, but reverts to the Reset state on its own in a time period controlled by an external RC circuit.

The 74122, and 74123, are Retriggerable Monostable Multivibrators. That is the timing period can be extended by triggering it again before the timing period ends, starting the timing period all over again. These also have a Clear input that over rides the timing cycle and clears the latch.

Some devices have a built in resistor in the timing circuit that may be used at the choice of the designer.

74145 BCD to Decimal Decoder. (see 7445)

Active low out, OC, 15 VDC, 80 mA.

A BCD code on the input selects one of the outputs to be active (low).

74180 8 bit odd and even parity generator and checker.

A parity scheme is used to give a confidence check for the integrity of data by evaluating the number of ones in a byte and controlling the overall number so it is odd (in odd parity), or even (in even parity).

When a byte is stored in memory a parity generator checks the number of ones in the byte. If there is an even number a ones, a ninth bit is stored in memory (a one) to make the whole odd. If there is already an odd number of ones, the ninth bit stored is a zero.

When the byte, and its parity bit is read from memory parity is checked again to see if it is odd (which it should be). If an even number of ones is read from memory, it can be assumed that a memory error has occurred. This is an Odd Parity Memory Scheme.

Likewise, an Even Parity scheme makes sure an even number of ones are stored and checked for when read.

Which one is best depends on the design of memory. If a massive memory failure (power lost to the memory array) occurs resulting in all zeros being read from memory, an Odd Parity scheme is called for. If a massive memory failure results in all ones being read from memory, an Even Parity memory scheme would be better.

This same scheme can be used in digital communication systems. The data transmitted is sent with Odd Parity (most common), and check when received to be sure it has Odd Parity.

This is not a perfect system. It will catch single bit errors with a high enough degree of efficiency, but there is always the possibility of two bits being in error leaving an erroneous odd parity. (For a better scheme, see Error Detection and Correction.)

74181 Arithmetic and Logic Unit (ALU), and Function Generator.

This IC performs Arithmetic operations (A plus B, etc), Logic Operations (A ANDed with B), and acts as a function generator (generates specific values, regardless of inputs, zero, one, negative one, etc.).

There are three sets of four inputs. A and B inputs are the two data inputs to be worked on. F inputs select one of 16 operations to be executed. The M (Mode) input selects Arithmetic or Logic operations. The 74181 can do 16 Arithmetic, or 16 Logic functions, but it is worth noting that not all functions have valuable results. Operations may be done in Active High logic, or Active Low logic, with the result of the 16 operations being different. For purpose of explanation, the Active High operations are used as examples. There is also a Carry In input that would be tied to Carry Out of the previous stage. The following Table shows a typical application.

The outputs are a set of four S outputs, the Sum or result of the operation. Carry Out, Carry Generate, and Carry Propagate.

If the arithmetic operation generates a Carry (sum is greater than F, or 1111), Carry Out, and Carry Generate goes high. If the result of the operation results in F, or 1111, then Carry Propagate goes high, indicating that this stage will not absorb a Carry from a previous stage. Normally this IC is cascaded to make operations in multiples of 4 bits. Four 74181s cascaded makes up a 16 bit minicomputer, such as a PDP-11 by Digital Equipment Corp.

When more than two 74181s are cascaded, a 74182 (Look Ahead Carry Generator) is used to speed up the operation. Carry Propagate and Carry Generate are fed to the 74182, the 74182 outputs go to higher stages of 74181s, etc. (See the data sheet for a typical application.)

Active High operation, Mode - 0 (Arithmetic Mode)

S inputs Output result

(3210) S outs

0000 A (plus Carry In)

0001 A plus B (plus Carry In)

0010 A plus complemented B (A minus B)

0011 A minus 1 (2's complement math)

0100 ?

0101 ?

0110 A minus B, minus 1

0111 ?

1000 ?

1001 A plus B, no carry

1010 ?

1011 ?

1100 A plus A (A shifted left (up) one position)

1101 ?

1110 ?

1111 A minus 1

Active High operation, Mode - 1 (Logical Mode)

S inputs Output result

(3210) S outs

0000 A negated, A not

0001 A ORed with B, negated

0010 A not, ANDed with B

0011 Logical zero value

0100 A ANDed with B, negated

0101 B negated, B not

0110 A ExORed with B

0111 A ANDed with B not

1000 A not Ored with B

1001 A ExORed with B, negated

1010 B

1011 A AND B

1100 Logical 1 generated

1101 A ORed with B not

1110 A ORed with B

1111 A

(ref. CPU12A.SCH)

This is the heart of a 12 bit microprocessor. U1, U2, and U3 make up the ALU using three 74181s. U4, U5, and U6 make 16 working registers (each is a 16 address by 4 bit register array). Together these are referred to the B Register. U20, U21, and U22 make up an Accumulator (where the results of all operations ends up). The 74181s get their A and B inputs from the Accumulator and the B register. The instructions for the ALU come from the Instruction Register (U11, U12, and U13) and the Instruction Decoder (U14). U17B holds the Flags that indicate the results of the operations, the Status Register.

Not indicated here is Program memory where instructions come from, and Data Memory (RAM). The contents of Program memory come in on the DATA BUS and are routed to the Instruction Register. Data also comes in on the DATA BUS, but is routed to one of the B Registers. The instructions tell the ALU what operation to perform between one of the B Registers and the Accumulator (the resulting data from the last operation.)

This is not a fully functional scheme, but it is close enough to functional to explain how these parts can be hooked together to make a processor out of TTL devices.

74184 Bi-Quinary to Binary converter

As the name implies, this circuit converts a bi-quinary five bit value (divide by 2, and divide by 5) code to a true binary value.

IN OUT

0 0 000 00000

0 0 001 00001

0 0 010 00010

0 0 011 00011

0 0 100 00100

0 1 000 00101

0 1 001 00110

0 1 010 00111

0 1 011 01000

0 1 100 01001

1 0 000 01010

1 0 001 01011

1 0 010 01100

1 0 011 01101

1 0 100 01110

1 1 000 01111

1 1 001 10000

1 1 010 10001

1 1 011 10010

1 1 100 10011

74185 Binary to B-Quinary converter

As the name implies, this circuit converts a true binary value, of 5 bits, to an 8 bit bi-quinary code.

IN OUT

00000 0 000 0 000

00001 0 000 0 001

00010 0 000 0 010

00011 0 000 0 011

00100 0 000 0 100

00101 0 000 1 000

00110 0 000 1 001

00111 0 000 1 010

01000 0 000 1 011

01001 0 000 1 100

01010 0 001 0 000

01011 0 001 0 001

01100 0 001 0 010

01101 0 001 0 011

01110 0 001 0 100

01111 0 001 1 000

10000 0 001 1 001

10001 0 001 1 010

10010 0 001 1 011

10011 0 001 1 100

10100 0 010 0 000

10101 0 010 0 001

10110 0 010 0 010

10111 0 010 0 011

11000 0 010 0 100

11001 0 010 1 000

11010 0 010 1 001

11011 0 010 1 010

11100 0 010 1 011

11101 0 010 1 100

11110 0 011 0 000

11111 0 011 0 001

74259 8 bit Addressable Latch

This is a register of eight latches which can be set or reset one at a time. The 74259 has three select inputs (S0, S1, and S2) to indicate which bit position is being referenced, a Data input to say to which state that latch is to be set, and a G input which is an Enable.

To set latch 2, put an input code of 010, set the Data input High, and enable the G input.

The Clear input is asynchronous (does not have to be accompanied with the G enable), and clears all eight latches.

74279 Quad S-R Latch

(ref. DEM74279.SCH)

The 74279 is four completely independant S-R latches. Each has a Set input and a Reset input (two of them have two Set inputs). Each latch has only one output, Q. DEM74279 shows a typical application for this circuit. The latches are used to remove the bounce of the contacts on the switches.

APPENDIX

What to do with unused inputs, and why. ---------------- A

Why you can't tie Totem-Pole outputs together. --------- B

Note on CMOS part numbers in the 74xxx series. --------- C

Power Supply requirements for TTL. --------------------- D

Glossary. ---------------------------------------------- E

Appendix A.

Unused Inputs

Most inputs have a diode in the input that prevents the input from exceeding VCC, or going more negative than ground. This is part of the architecture of the substrate. Under many circumstances, unused inputs have been tied directly to VCC. This is not a good practice. Failure can occur, and finding out which input failed on a board of 100 ICs isn't a pleasant thought.

Better ideas

1) Connect unused inputs to an independent supply voltage of 3.5 to 4.5V.

2) Connect them to another input of equal function. Such as tying both inputs of a NAND together to make it an inverter (in stead of tying it high by some other method). Watch out for loading characteristics when using this method. Make sure the driving IC can handle the extra load.

3) Connect it to VCC through a resistor. The value of the resistor isn't doesn't have to be very specific. 1K for 74xx, a little lower for 74Hxx and 74Sxx, up to 10K for 74Lxx, 74ALSxx.

This method gives you the most flexibility for troubleshooting. The input tied to a pull up resistor can be used to note a bad device, or may be used to input a signal for troubleshooting.

4) Connect them to an output that never goes low. Watch fanout so you don't over drive the gate. This is a good application for unused gates on the board. Tie the input of a unused Inverter to ground and use the output to tie unused inputs to.

Don't let them float. An unused input floats to about 3 V, and can act as an antenna, picking up stray signals. Real unpredictable, because this may not happen on the manufacturing floor, but in the field the environment may have more noise.

Appendix B

Why you can't tie Totem-Pole outputs together.

Referring to drawing NAND.SCH, if two such devices are tied together and one is outputting a High (Q3 on) while the other is outputting a Low (Q4 on) what we have is essentially a short from GND to VCC through the two transistors. Q3 is partially protected by R4 and D3. Q4 is usually the first to melt.

It is worth noting that Q3 is protected sufficiently to allow troubleshooting of circuits by shorting outputs to ground. Do this with certain TTL families only. 74xx, 74LSxx, or 74Lxx can be done with some degree of safety. Other TTL families are not so forgiving, and never do it with Advanced devices (74ASxx, 74ALSxx, etc), and especially not CMOS devices of any kind.

Appendix C

NOTE: Not all parts with 74xxx numbers are TTL. 74Cxx, 74HCxx, 74HCTxx, and anything with a C in the number are CMOS architecture, not TTL. These usually have the same pinout and function as the TTL device with the same number (USUALLY).

Appendix D

Typical VCC is 5.0 VDC. Absolute max VCC is 7.0 VDC, but VIN should not exceed 5.5 V, in any case.

Open collector devices can drive voltages higher than VCC. Normally this is about 7.0 VDC. (7416, 7417, and 7426 can drive to 15 VDC; 7406, 7407 can drive to 30 VDC.)

Appendix E Glossary

Adder - A circuit that performs addition between two values. Half Adders do not take into condition Carries to the next higher bit. Full adders do.

Addressable Latch - A latch in which each bit is address individually.

ALU - Arithmetic and Logic Unit. The processing central part of a CPU.

Ambient Temperature - The temperature of the surrounding air. It is worth noting that ambient temperature does not realistically indicate the temperature of the chip. Keep in mind that the actual circuitry is inside the IC package, encased in plastic.

Analog - A circuit whose voltage is adjustable, or changing. Audio or Radio circuits are analog, as opposed to digital.

AND Gate - A circuit that simulates the AND operation. "This" and "That" must be present before the out can happen.

AND-OR-Inverter - An array of gate with AND gates on the inputs. The output of the AND gates feed to an OR gate. (Any AND gate with satisfied inputs gives a true output.) The output usually has True and Complement outputs (the Invert).

Asynchronous - Does not have to happen in association with a clock pulse. Preset and Clear inputs to latches, etc.

BCD - Binary Coded Decimal. A four bit binary code that represents the numbers 0 (0000) through 9 (1001). A partial subset of Hexadecimal.

Binary - A numbering system made up of 0's and 1's only, and thus, easy to implement into digital logic.

Binary Coded Decimal - (see page, this heading)

Bi-Quinary - (see page, this heading)

Bi-stable - Having two stable states. A Latch is bi-stable. It can be Set, or Clear, and stays that way after the inputs have gone away.

Blanking - A method of turning off insignificant zeros in a string of numbers. Zero Suppression.

Buffer - 1) A non-inverting single input gate. Used to isolate two circuits, but still allowing communication. Oscillators usually have a Buffer stage on their output to keep the circuitry from loading down the oscillator. 2) A gate with a high current output used to drive heavier than normal loads. May or may not, invert. May our may not be capable of higher than normal output voltages.

Clamp - A circuit (sometimes as simple as a diode) that limits the voltage at a certain point to not more than a specific voltage.

Clock - 1) An oscillator, or its signal, that provides a necessary frequency to a circuit. 2) An input to a latch, counter, etc, that is a timing strobe.

CMOS - Complementary Symmetry Metal Oxide Semiconductor. A logic family whose basic logic cell is made of a P-MOS transistor that drives to a positive rail, and a N-MOS transistor that drives to ground (or a negative rail). Draws very little current compared to TTL devices, but are much more sensitive to static electricity.

Counter - A set of latches wired such that they provide a coded output upon subsequent clock pulses.

D - Type Flip Flop - A basic Flip Flop that has a Data input (D), and a Clock input (C), as opposed to a J-K type. May, or may not, have Preset or Clear inputs that over ride the D and C inputs.

Darlington - A two transistor circuit whose gains multiply. When the input transistor turns on, it turns on the output transistor.

Decade - Having ten states. A Decade counter counts from 0 to 9, then starts again at 0.

Decoder - A circuit that takes an encoded multiple bit pattern, and whose outputs are only active one at a time.

Demultiplexer - A circuit that decodes multiplexed signals.

Digital - A system that is configured of logic circuits that are either on or off, as opposed to analog.

Divide by N - A counter with a flexible design that allows it to count in different patterns.

Driver - A gate or output capable of driving to unusually high currents or voltages.

DTL - Diode Transistor Logic. The diodes on the input provided the logical AND functions, and transistors inverted the signals, or just restored them to good logic levels.

Dual - Having two sections. A Dual 4 Input NAND gate has two NAND gates per package, each with four inputs.

Edge Triggered - A latch, register, or input that activated on the rising or falling edge of a clock pulse.

Enable - A non-data input must be satisfied before a function can happen.

Encoder - A circuit that takes one of many inputs (or simple inputs) and outputs a coded value appropriate to that input. (see Keyboard Encoder, or Priority Encoder.)

Exclusive NOR Gate - A gate that outputs a low when the inputs are not equal to one another.

Exclusive OR Gate - A gate that outputs a high when the inputs are not equal to one another.

fmax - Maximum clock frequency.

Fan In - The amount of current an input draws. Instead of being measured in current, it is compared relative to the standard 74xxx TTL input, in Unit Loads.

Fan Out - The amount of current an output can sink (High output) or source (Low output). Instead of being measured in current, it is compared relative to the standard 74xxx TTL output, in Unit Loads.

Flip Flop - A circuit that has two stable states, and retains what ever state is was last put in after the input goes is removed. A.K.A. Latch.

Gate - A simple circuit that performs, a non-latching logic function. AND, OR, Invert, Buffer, etc.

Hex - 1) Short for Hexadecimal (having sixteen states); 2) Having six sections to it, as a Hex inverter (7404).

Hexadecimal - A four bit code that represents a value from 0 (0000, or o) to 15 (1111, or F). (see page, this heading)

Hold Time - The amount of time an input must be in an active stable state for the circuit to fully recognize it.

ICC - Typical supply current for VCC.

ICCH is with all outputs High.

ICCL is for all outputs Low.

IIH - Input current with a High in.

IIL - Input current with a Low in.

Inverter - A circuit that turns a High into a Low, or Low into a High. (see 7404)

IOH - Output drive current capability with a high out.

IOL - Output drive current capability with a Low out.

IOS - Output current with the output shorted to ground and attempting to drive High.

J-K Flip Flop - A Bi-Stable latch that has two data inputs. J on the Set side, K on the Reset side. In order to set the latch J must be high and K must be low when it receives the clock pulse. To clear it J must be low and K must be high when it receives a clock pulse. If both are low, the clock input has no effect on the latch. If both J and K are high, the latch toggles (if it was set, it resets. If it was reset, it sets. Inputs are named after the engineer's initials (John Kardash).

Latch - A circuit that has two stable states, and retains what ever state is was last put in after the input goes is removed. A.K.A. Flip Flop.

Leading Zero Suppression - A blanking scheme to turn off digits that are zeros to the left of the most significant digit representing a number.

Level Triggered - A latch or register design that allows the output to follow the input while the clock is active. When the clock is removed the output stays in what ever state it was last in. A.K.A. Transparent Latch.

Look Ahead Carry Generator - Circuitry added to an ALU or Adder to speed up Carries from one stage to another. Instead of rippling through the Adder, the Carry signals are moved from stage to stage more quickly by viewing the overall state of the ALU, or Adder.

Magnitude Comparator - A circuit that not only compares two values to be equal, but also gives their relative relationship to one another. Outputs are AB.

Master-Slave Flip Flop - Two level triggered latches cascaded together and each operating off a different level of the clock. One is the input (Master) whose outputs feed to the inputs of the other (the Slave) which supplies the outputs of the circuit. For example, when the clock on the Master latch goes high data is latched into the Master latch. When the clock goes low the condition of the Master Latch is transferred to the Slave Latch.

Monostable - A latch having only one stable state (Reset). Once Set it eventually reverts back to the Reset state, depending on an external RC time constant. A.K.A. Single Shot.

Monotonicity - The characteristic of a signal to not change direction during transition periods. (see listing under DACs)

Multiplexer - A circuit that puts multiple signals on one line.

Multivibrator - A circuit (latch) that changes states on its own. Either Monostable, or Astable.

NAND Gate - A basic gate whose output is low when all inputs are high.

NMOS - N channel Metal Oxide Semiconductor. (Arrow pointing towards the channel.) When the gate is brought high it turns on.

NOR Gate - A basic logic gate whose output is low when any input is high.

Octal - 1) A base-8 number system that counts from 0 to 7 in each digit position. 2) Having eight sections to it, as in Octal latch, or Octal buffer.

One Shot - A Monostable Multivibrator (see listing, this heading).

Open Collector - An output that has no transistor to pull up to the high rail (VCC). Made for driving abnormal loads, or wiring more than one output together to make a WIRED-AND.

OR Gate - A basic logic gate whose output is high when any input is high.

Parallel - Having multiple data inputs and outputs transferred at the same time.

Parity Checker / Generator - (see listing, this heading)

PMOS - P channel Metal Oxide Semiconductor. (Arrow pointing away from the channel.) When the gate is brought low, it turns on.

Propagation Delay - The time it takes for the effects on in input to be apparent at the output. The time it takes for the signal to propagate through the gate, latch. or ...

Pulse Width - The time a pulse is measurably active. A positive going pulse is measured from the time it reaches the legal High level to the time it falls below the legal high level.

Quad - Having four parts. Like a 7400 is a Quad 2 input NAND.

Race Condition - The condition where the inputs of a gate or latch are not timed in proper sequence. In a latch the data should be active and stable for a certain time before the clock signal occurs. The same can happen in complex, or high speed, gate circuits.

RAM - Random Access Memory. It can be wrote to or read from. The name comes from antiquity. Once was a time that memory was stored in a rotating drum media. You had to access memory sequentially and wait for your data to come around. RAM was named in contrast to the sequential type of memory.

Receiver - An incoming signal, as the local processor views it.

Register - A parallel array of latches.

Register File - An array of registers.

Retriggerable - Indicates that the circuit can be triggered again, starting a timing period over again when it has not yet completed its timing period.

Ring Counter - A series of latches in which only one bit is set at a time. When it gets a clock, that latch clears and the next latch in the string sets. When it gets to the end of the string, it starts all over again at the lower bit.

Ripple Counter - A counter where a lower stage toggling goes to the clock of the next higher stage and toggles it, which toggles the next higher stage, which toggles the next higher stage. (see listing, this heading)

Ripple Blanking - A zero suppression display method that turns off displays with insignificant zeros.

RTL - Resistor Transistor Logic. An old family of logic typified by resistors doing the ANDing function.

SAR - Successive Approximation Register. A register used in an Analog to digital converter. Data is shifted into the register. Whether a 1 or 0 is shifted in depends on how the input voltage compares with a reference.

Schmitt Trigger - An input configuration that narrows the window between what is defined as a valid high and low. There is also a hysteresis characteristic to the input to help remove glitches caused by signals that exhibit non-monotonicity.

Schottky Transistor - A transistor made with a high speed diode across the Base and Collector junction preventing the transistor from going too deep into saturation. It is the burden of coming out of deep saturation that slows down digital circuits.

Serial - A method of moving data one bit after another, as opposed to in parallel.

Setup Time - The required time that data must be present and stable before the clock signal comes up.

Seven Segment Display - A display made of seven light emitting segments, three horizontal, and two vertical along either side. Capable of displaying decimal, hexadecimal, and a very limited set of letters. What character will be displayed is dependant on the driver that turns on the segments.

Shift Register - A register capable of shifting bits from one stage to another. (see listing, this heading)

Strobe - An input to a circuit that is not a data value, but an enable to allow something to happen. Inputs are strobed, outputs are enabled (but this concept is not universal).

Subtractor - An arithmetic section that subtracts one value from another. This subtraction is usually done by inverting the subtrahend and adding it to the minuend.

Successive Approximation Register - (see SAR)

S-R Latch - The most basic of latches made of two gates.

Synchronous - Happening in coordination with a clock pulse.

Toggle - To change a latch from one state to another. Set to Reset or Reset to Set.

Totem-Pole - An output configuration that has active circuits pulling to both rails (VCC and Ground).

TTL - (see listing, this heading)

Trailing Zero Suppression - A display method that turns off zeros lower that the least significant digit.

Transceiver - An output that is capable of driving or receiving.

Transition time - The time it takes a leading or trailing edge of a pulse to actually change states. It is during this time that most of the current is drawn in logic circuits because both high drive and low drive transistors are on to some degree. Higher frequencies spend a higher percentage of their time in transition, ergo, draw more current, generate more heat, ...

Transmitter - An output stage, as viewed by the local processor.

Transparent Latch - A latch or register design that allows the output to follow the input while the clock is active. When the clock is removed the output stays in what ever state it was last in. A.K.A. Level triggered.

Trigger - A clock input that activates a function.

Tri-State - An output circuit design capable of outputting a High, Low, or a high resistance to both rails (the Tri-state condition).

Unit Load - (see listing, this heading)

VIH - Minimum input voltage that will be recognized as a High.

VIL - Maximum input voltage that will be recognized as a low.

VCC - In TTL, +5 VDC (4.75 VDC to 5.25 VDC).

VCO - Voltage controlled oscillator. An oscillator whose frequency is controlled by an incoming analog signal.

Wired AND - A circuit where open collector outputs are connected together. All inputs must be High before the output can be High.

Wired OR - A circuit where open emitter outputs are connected together. Any input being High will result in the output being High.

Zero Suppression - Turning off displays containing zeros that are higher than the most significant digit, or lower than the least significant digit.

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