Overview - Global Semiconductor Alliance



00GSA MEMSProcess Design DocumentationQuality ChecklistVersion 0.5 | June 16th 2014MEMS PDD QUALITY CHECKLISTChecklist FormVersion 0.5Insert Your Company Logo Here HYPERLINK \l "_What_is_the"OverviewThe GSA MEMS Process Design Documentation (PDD) Checklist is a document completed by PDD developers and delivered with each new release of MEMS process design documentation. HYPERLINK \l "_Section_1_–" 1. Foundry and Support Contact InformationFoundry & Process Information Foundry Name__________________________________________Process Name__________________________________________PDD Documentation Name & Version_______________________________PDD Documentation Date______________________________________PDD Checklist Revision ____________________________________PDD Support Contact (Specify how PDD users should contact foundry for questions & issues; customize this section as needed.)Name__________________________________________Phone__________________________________________Email or URL__________________________________________ HYPERLINK \l "_Section_2_-" 2. Foundry Process Documents Document InformationDocument Number & TitleSectionRevisionDateResponsibleWafer informationBow/Warp ExpectationsDoping levelEdge ProfileThickness ToleranceSurface RoughnessPassivation TypeWafer Layout InformationAlignment marksWafer Numbering ConventionWafer Scribe InformationDicing StreetsDie Layout MapDie Numbering ConventionsProcess InformationContamination/Quarantine Policies Mask sense information or Resist Sense informationMask biasingStress ProfilesTemperature budgetProcess Control Monitor (PCM)Layout InformationBonding Pad RulesChip Finishing InstructionsDesign Layout RulesLayer MapTapeout InstructionsMask ProcurementDevice DesignsDesign Manual (PDD Devices)PDD Device Cross SectionsMapping between process modules & PDD devicesSafe Operating Area (SOA)PackagingAssembly and HandlingWafer handling –manual vs. AutomatedTest and MeasurementWafer level test structuresElectrical RulesElectrical ParametersElectrical Rules CheckingElectromigration Parameters (current density)ESD GuidelinesInterconnect SpecificationLatchup RulesMatching ModelsNoise ModelPcell DocumentationProgrammable Electrical Rules Checking (PERC)RF Parameters/ModelingSPICE Model ChecklistSPICE Model Library(Rows can be added as needed. No rows should be removed, however. Use N/A if not applicable.) GSA MEMSPDD QUALITY CHECKLISTUsers GuideVersion 0.5 HYPERLINK \l "_Overview" What is the MEMS PDD Checklist?The GSA MEMS Process Design Information (PDD) Checklist is a document completed by the PDD developers and delivered with each new release of a MEMS process design information. This document contains a summary of the PDD, including relevant contact information and foundry process and design documents.This document serves as a combination ingredients list and “nutrition facts label” for MEMS PDD. This document helps you obtain a better understanding of the source data, completeness and quality of the PDD before using it to design MEMS.Understanding and Using the Sections of the PDD Checklist HYPERLINK \l "_1._Foundry_and" Section 1 – Foundry and Support Contact InformationThis section describes how to contact the foundry if questions arise relating to the PDD.Foundry Name – name of foundry company and fab location (or number if relevant).Process Name – process code and modifiers that uniquely define the process and all process options that could affect the model or differentiate the model from another process derivative.PDD Name & Version - name of PDD and version that uniquely defines this PDD release.PDD Date - date of PDD releasePDD Checklist Revision - Indicates revision of the PDD checklist document itself (in case you may need to revise just the PDD document, but the PDD itself didn't change).PDD Support Contact – how to contact the foundry if questions arise relating to the PDD. It may contain a Web site URL, name, phone, fax and/or e-mail. Customize this section as needed. HYPERLINK \l "_2._Foundry_Process" Section 2 - Foundry Process DocumentsThis section includes references to: (1) foundry documents used to create the PDD or needed to design with the PDD; (2) documents describing the source of data used in the PDD; or (3) the methodology and tradeoffs used to obtain PDD data. Each foundry has a different method of naming and bundling these documents into single or multiple subject documents.Document Number & Title – identifier that is used to link the document and the process, and its derivatives.Section – describes which volume or section (used when foundries put many of the documents described in this section into a single manual). Revision – many foundries use a version numbering system (0.X for pre-production, 1.X for risk production and 2.X for full production) of a model or document.Date – release date of the document or data file.Description of Document Information (listed in alphabetical order):Alignment Marks – document (if separate or if in a single design manual, which section) that addresses how alignment marks are placed on the wafer. Bonding Pad Rules – document (if separate or if in a single design manual, which section) that addresses rules and guidelines for layout pad structures supported by the foundry. Bow/Warp Expectations – document that addresses the bow/warp specifications supported by the foundry.Chip Finishing Instructions – document (if separate or if in a single design manual, which section) that addresses requirements by the foundry for special layout structures, die seal, etc. to be included in the chip database prior to tapeout. Contamination/Quarantine Policies – document (if separate or if in a single design manual, which section) that addresses the contamination and quarantine policies of the foundry. Design Layout Rules – document (if separate or if in a single design manual, which section) that addresses the layout geometry rules for the process. This document (or a separate document) may include the electrical rules or process control monitor (PCM) specification for the process and the design rule checking (DRC)/layout vs. schematic (LVS)/layout parameter extraction (LPE) runset that interprets and verifies the latest design rules (often a separate foundry document).Design Manual – name of a document that includes the design layout rules, layer map, DRC, LVS, LPE and parasitic runsets. Device Cross Sections – document (if separate or if in a single design manual, which section) that includes cross-section drawings for each PDD device.Dicing Streets – document (if separate or if in a single design manual, which section) that describes how the dicing streets are laid out on the wafer.Die Layout Map – document (if separate or if in a single design manual, which section) that includes drawings of the die layout map.Die Numbering Conventions – document (if separate or if in a single design manual, which section) that describes any die numbering conventions.Doping Level – document (if separate or if in a single design manual, which section) that specifies the wafer(s) doping level.Edge Profile – document (if separate or if in a single design manual, which section) that includes the edge type and finishing of the wafer(s).Electrical Parameters – document (if separate or if in a single design manual, which section) that defines the key device electrical parameters for design.Electrical Rules Checking - document (if separate or if in a single design manual, which section) that defines rules that check for electrical connections in the circuit that are considered dangerous. These may include checks for unconnected inputs or shorted outputs, ESD issues, voltage dependent rules, etc.Electromigration parameters - document (if separate or if in a single design manual, which section) that defines parameters such as current density that are used during the layout implementation to reduce electromigration damage during operation of the chip. Electrostatic Discharge (ESD) Guidelines – guidelines that define the appropriate structures to be used to achieve various levels of ESD tolerance.Interconnect Specification – document (if separate or if in a single design manual, which section) that defines interconnect parameters such as resistance and capacitance used by parasitic extraction. Latchup Rules – document (if separate or if in a single design manual, which section) that addresses rules to prevent circuit latchup. Layer Map – document (if separate or if in a single design manual, which section) that addresses drawn layers, colors and stipple patterns used to describe the layout for the layout editor, DRC, LVS and parasitic extraction tools.Mask Biasing – document (if separate or if in a single design manual, which section) that addresses any biases applied to masks before use in the fabrication process by the foundry.Mask Procurement – document (if separate or if in a single design manual, which section) that addresses requirements for mask making, including the relationship between drawn PDD layers and the actual masks. Mask Sense Information – document (if separate or if in a single design manual, which section) that addresses the mask or resist sense- clear field/dark field or positive/negative resist. Matching Models – document (if separate or if in a single design manual, which section) that addresses local process variation and mismatch (LPVM) issues.Noise Model – document (if separate or if in a single design manual, which section) that addresses noise model issues.Passivation Type - document (if separate or if in a single design manual, which section) that describes the passivation used on the Wafer. Pcell Documentation - document (if separate or if in a single design manual, which section) that describes the interface of the Pcells. Process Control Monitor (PCM) – PCM parameters provided by the foundry to define the acceptable process corners for wafer acceptance.RF Parameters/Modeling – document (if separate or if in a single design manual, which section) that addresses RF parameters and modeling issues.Safe Operating Area (SOA) – document (if separate or if in a single design manual, which section) that addresses the voltage and current conditions over which the PDD devices can be expected to operate without self-damage.SPICE Model Checklist – reference to the GSA Mixed-Signal/RF SPICE Model Checklist(s) that describe(s) the details of the SPICE models used in the PDD.SPICE Model Library – all model files (.lib or separate model cards). Surface Roughness - document (if separate or if in a single design manual, which section) that describes the surface roughness spec of the wafer. Stress Profiles – document (if separate or if in a single design manual, which section) that addresses the stress profiles found on the layers as deposited.Tapeout Instructions - document (if separate or if in a single design manual, which section) that describes the procedures for taping out chips designed with this PDD. Temperature Budget - document (if separate or if in a single design manual, which section) that process temperature limits. Thickness Tolerance - document (if separate or if in a single design manual, which section) that describes the thickness tolerance of the wafers. Wafer Numbering Convention- document (if separate or if in a single design manual, which section) that describes how wafers are numbered. Wafer Scribe Information- document (if separate or if in a single design manual, which section) that describes how the wafers are scribed. PDD Checklist FeedbackPlease send feedback on the usability and clarity of the GSA MEMS PDD Checklist and/or Users Guide to the GSA Working Group Manager (hbeasley@; 972-489-0248)AcknowledgementsGSA wishes to acknowledge the contributions of the following people for their significant contribution and effort to develop and review the GSA MEMS PDD Checklist.Mary Ann MaherMaarten VraanesHarrison Beasley, GSARevision HistoryMEMS PDD Checklist (Version 0.5)June 2014 – initial creation of documentImportant DisclosuresCopyright? 2014 by GSA. All rights reserved. GSA grants a worldwide license to all PDD developers to add data, contact information and company logo to a copy of the GSA MEMS PDD Checklist and distribute it to their partners, prospects and customers; however, all references to GSA, including GSA logo and GSA references may not be altered in any way. GSA makes no claims to the accuracy of the data entered on a GSA MEMS PDD Checklist. ................
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