Active – HDL Overview



Active – HDL Overview

Aldec’s Active – HDL is a popular software verification tool created for the sole purpose of facilitating the certification of HDL codes in a simple, powerful and reliable way. The software creates a user-friendly platform with the ability to perform simulations of our code, so the designer can verify the codes effectiveness.

The software’s simplicity enables us to quickly generate subjective tests with little or no hassle (put our code to numerous tests, also known as simulations, which verify the validity of the generated code.) This overview will get the user acquainted with the software, and its basic testing procedures.

In order to achieve this, we will have to follow these simple steps:

1. Double click on the “Active – HDL” icon in Windows Desktop or go to Programs/Active-HDL 5.2.

2. Select “VHDL Design Entry” in the next selection menu.

3. Select “Create a New Workspace” so that a new design can be started. This workspace can contain numerous HDL codes, so it would be wise to select a suitable name for the project, one that can be easily remembered later.

4. In the “New Design Wizard” screen select “Create an Empty Design” and choose the following settings:

• Select “Synplicity Synplify Pro 7.x” as the synthesis tool.

• Select “Xilinx ISE 4.x” as the implementation tool.

• Select “Xilinx-3.3 Spartan” as the default family.

5. Select a name for the design to be prepared and press “OK”.

6. Press “Finish” when done.

7. On the “Design Browser” seen on the left side of the screen, double-click on “Add New File”. Select “VHDL Source Code” and choose a new for the code to be written.

8. Write the desired code to be implemented in the new screen that appears.

9. Once the code is done, save the source code and click on the “Compile” icon found at the top of the screen to compile the file. The compiler lets you know of any errors or possible errors that the source code might contain. If more than one source code is present, select the “Compile All” option instead.

10. To begin the simulation of any source code, press the “New Waveform” icon that appears on top of the screen. Select the “Structure” tab on the Design Browser window. This tab shows all the entities that have been created on the current design. Select the entity that will be simulated. When an entity is selected, the Design Browser will show all the signals that are used by that entity.

11. Drag and drop the signals of interest to be seen during the simulation period onto the “Waveform Editor” screen. The signal should now be seen on the left column of the “Waveform Editor”.

12. To be able to simulate the code that has been written, all input signals must have “Stimulators” to simulate their behavior. To assign a “stimulator” to an input signal, right-click on the preferred signal and select “Stimulators”. A new menu showing the different type of signals that can be simulated should appear. These type of signals include:

• Clock – This signal type allows the signal to behave as a clock. This screen allows the user to select the frequency and duty cycle that the signal will have.

• Force Value – This signal type allows the user to “force” a value throughout the whole simulation. The “Forced Value” will be determined by the user, and can contain any number of bits as long as it matches the signal type.

• Counter – This signal type forces a periodically changing value. The count direction, starting value, step and period are all parameters predetermined by the user.

13. After selecting the different “stimulators”, select the “Simulation Time” desired and select the “Run for” button found just to the left of the “Simulation Time” slot. Press as many times as needed. Pressing this button will run the simulation for the selected time, and the resulting waveform will allow the user to see if the signals are behaving as they were intended. If they do not behave as expected, then the user can go back to the source code and modify it.

Synplify Tutorial

The Synplify Pro tool starts with all the features that made Synplify software the industry's most popular and robust synthesis product, and moves beyond by providing additional capabilities. By using the Synplify Pro solution, you can push the performance of challenging and complex designs while remaining comfortably on or ahead of schedule.

In order to achieve this, we will have to follow these simple steps:

1. Double click on the “Synplify Pro 7.0” icon in Windows Desktop or go to Start/Programs/ Synplicity/Synplify Pro 7.0.

2. Select “Open Project” and then “Project Wizard” so that a new project can be started.

3. In the “Project Wizard” screen select “Synthesis” in the select project type. Choose the name to identify your project and write it in the “Project Name” tab. Choose the desired location to save the project in the directory browser. Then press “next”.

4. Select “Add files” and select the vhdl files of your project. Make sure that the top-level hierarchy is in the bottom of the list. Then press “next”.

5. In the “Project Wizard- Select the target technology and the mapping options” window (Figure 1) choose the following settings:

• Select Xilinx Spartan in the “Technology” tab.

• Select XCS10 in the “Part” tab.

• Select “Speed” -3.

• Select PC84 “Packages”.

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Figure 1: Target Technology and Mapper Options Window

6. Select Next.

7. Type the name of the entity that encompasses the entire project at “Top Level Entity”. (Figure 2)

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Figure 2: VHDL Options Window

8. Press “Finish” and then “Run” when done.

9. Verify if there are any errors or warnings in the code.

10. Modify the source codes if there are any errors or warnings, save and press “Run”.

11. Repeat steps 8 through 10 until there are no errors or warnings. At the end you will have the .edf file to be “downloaded” on the FPGA.

Xilinx ISE 4

1. Double click on the Xilinx ISE 4 icon or go to Start/Programs/ Xilinx ISE 4/Accessories/Design Manager.

2. Select “File” and go to “New Project”. When the window appears, select the project EDF file in “Input Design”, and select the directory where the project will be saved in “Work Directory”. Add a comment and then press “OK”.

3. On the next window, type a name for the new version of the project and the new revision of the project in “Version Name” and Revision Name” respectively. Then press “OK” on the “Part Selection” window, and also in the “New Version” window.

4. Press the “Flow Engine” button to run, map and translate the entity (See Figure 1). On the window that appears click on the “play” button and wait until all the processes are completed (Figure 2).

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Figure 1: Design Manager Window

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Figure 2: Xilinx Flow Engine Window

5. Close the Flow engine window if there are no problems and the status is OK and the Design Manager Window (Figure 1) press the Constraints Editor button.

6. On the Constraints Editor Window press the “Ports” tab (Figure 3). Notice that all the signals that you have specified on your top-level hierarchy file appear on the Port Name column of the table.

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Figure 3: Constraint Editor Window/ Ports tab

7. Using Table 1 decide where those signals are going to be connected on the board. Then double click on the Location column and write the desired port on the location field with a p before the port number. For example if you want to connect a signal to the first switch on the board write p28 on the location field of that signal.

8. When all signals have been assigned close the window and repeat step 4. If there are no errors close the Flow Manager window.

9. Connect the parallel port to the computer and the power supply to the board. Press the iMPACT button. On this window select the Slave Serial tab. Right click and select “Cable Auto Connect”. When the connection is detected Right click again and select “Add Xilinx Device…” This will open a browse window, find the .bit file that was generated and click ok.

10. Right click the icon and press “Program…” wait for the Programming Successful message. If it appears test your application on the board.

Table 1: Pin assignment on the Digilab XLA5 Board [pic]

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