PDF Low Density Parity Check Code Implementation

Low Density Parity Check Code Implementation

Senior Project Final Report

Students: Matthew Pregara

Zachary Saigh

Advisors: Dr. In Soo Ahn Dr. Yufeng Lu

Department of Electrical and Computer Engineering Bradley University 05/2013 1

Table of Contents

Abstract ............................................................................................................................... 5 1. Introduction ................................................................................................................ 6 1.1 Objective................................................................................................................. 7 1.2 Project Description .................................................................................................. 7 1.3 Linear Block Coding................................................................................................ 8 1.4 LDPC Codes .......................................................................................................... 10 1.5 Log-Likelihood-Ratio Algorithm ........................................................................ 11 1.6 Functional Requirements ................................................................................... 14 2. Project Approach ...................................................................................................... 15 2.1 Simulink Design................................................................................................... 15 2.2 Pre-Implementation Challenges......................................................................... 15 2.3 Simulink Encoder Implementation .................................................................... 17 2.4 Xilinx Encoder Implementation ......................................................................... 19 2.5 Simulink Decoder Implementation.................................................................... 20 2.6 Constructing a Lookup Table ............................................................................. 22 2.7 Simulation Results............................................................................................... 23 3. Conclusion................................................................................................................. 38 3.1 Future Work......................................................................................................... 38 Appendix A ........................................................................................................................ 41

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Figures

List of Figures and Equations

Figure 1: FEC Code Performance Comparison .................................................................... 6

Figure 2: High level LDPC System Block Diagram ............................................................... 7

Figure 3: Hamming Code Block diagram............................................................................. 8

Figure 4a: Encoding for Linear Block Codes........................................................................ 9

Figure 4b: Modulo-2 addition used for parity bit calculations ........................................... 9

Figure 5: Tanner Graph with corresponding H matrix...................................................... 11

Figure 6: Tanner graph for a (10,5) code with received values ........................................ 12

Figure 7: Calculation for Edge between V1 and C1 ........................................................... 13

Figure 8: BER Comparison between different Iteration Numbers ................................... 14

Figure 9: Simulink LDPC System Model ............................................................................ 15

Figure 10: Low level Simulink Encoder ............................................................................. 17

Figure 11: Low Level Encoder Verifcation......................................................................... 18

Figure 12: Xilinx Encoder................................................................................................... 19

Figure 13: Xilinx Encoder Verifcation................................................................................ 20

Figure 14: Low Level Simulink Decoder ............................................................................ 21

Figure 15: Phi(x) Lookup Table Comparison ..................................................................... 22

Figure 16: Lookup Table Performance Comparison ......................................................... 23

Figure 17: Complete Lookup Table Function Block .......................................................... 24

Figure 18: Lookup Table Output ....................................................................................... 25

Figure 19: Lookup Table Memory ..................................................................................... 25

Figure 20: Index Cap Block ................................................................................................ 26

Figure 21: Lookup Index Number ..................................................................................... 26

Figure 22: Absolute Value Function.................................................................................. 27

Figure 23: Edge Calculation Block ..................................................................................... 27

Figure 24: Edge Cycle Through System ............................................................................. 28

Figure 25: Max Count Block .............................................................................................. 29

Figure 26:Product/Sign Block............................................................................................ 30

Figure 27: Summation Block ............................................................................................. 30

Figure 28: Edge Calculation Blocks that make up a Node ................................................ 31

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Figure 29: Total Check Node View .................................................................................... 32 Figure 30: Zoomed-In Check Node View .......................................................................... 32 Figure 31: Full Decoder in Xilinx........................................................................................ 33 Figure 32: Variable Node Calculation Blocks .................................................................... 34 Figure 33: Variable Node Calculation Block Internal View ............................................... 35 Figure 34: Complete Decoder System .............................................................................. 36 Figure 35: Received Codeword Block Internals ................................................................ 37 Figure 36: Control/Timing Block ....................................................................................... 38

Equations

Equation 1: Phi Function................................................................................................... 13 Equation 2: Square Add Function ..................................................................................... 16 Equation 3: Max* Function ............................................................................................... 16

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Abstract

In communication systems, forward error correction (FEC) codes have been widely used to battle data errors caused by transmission through a noisy channel. By adding extra bits to the end of message bits, a certain number of bit errors can be detected and corrected without frequent retransmission. Low density parity check (LDPC) is a powerful FEC coding scheme which can achieve good error performance under very low signal-to-noise ratios [1]. A communications system utilizing LDPC code is able to get very close to the channel capacity limit established by Claude Shannon in the 1940's. In addition, LDPC codes have lower complexity in the decoding process compared to other FEC codes. With advances in computing power, LDPC codes have been adopted in many high speed communication standards such as digital video broadcasting, WiMAX, 4G wireless systems, among others.

This project explores the process as well as the feasibility of implementing the design of a LDPC system on a field programmable gate array (FPGA). The Xilinx System Generator block set is used in conjunction with MATLAB and Simulink for FPGA cosimulation.

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1. Introduction

In digital communication systems, there are two different ways commonly used to reduce errors caused by a noisy channel. One is called Automatic Repeat request (ARQ). With ARQ, a receiver is able to detect if a message was received in error. If an error occurred, the receiver sends a request back to the transmitter to repeat the message that was in error [1]. This method of error correction requires a two-way channel and is not a feasible method for one-way systems such as digital video broadcasting.

Another way to reduce errors in a communication system is to use a Forward Error Correction (FEC) scheme. The FEC scheme adds redundant information to a message in the form of extra bits called parity bits. Using this redundant information, the receiver is able to detect and correct a message without requesting a retransmission [1].

Low density parity check (LDPC) codes are a powerful FEC coding scheme that can achieve good error performance under very low signal-to-noise ratios. A communication system utilizing an LDPC code is able to operate very close to the channel capacity limit established by Claude Shannon in the 1940's [2]. Figure 1 compares the performance of various coding schemes used in the communication industry. It shows that LDPC codes achieve the same code rate of 0.5 as many other codes. It can operate close to the Shannon Capacity Bound in a lower signal power environment.

Figure 1: FEC Code Performance Comparison [3]

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In addition to their good performance, LDPC codes have lower complexity in the decoding process compared to other FEC codes such as Turbo codes [3]. LDPC codes were developed in 1960 by Robert G. Gallager at MIT. With recent advances in parallel computing power, LDPC codes have been re-discovered and studied. They are used in many high speed communication standards such as digital video broadcasting, WiMAX, 4G wireless systems, to name a few [2].

1.1 Objective

The project aims to explore the use of Field Programmable Gate Arrays (FPGAs) in the encoding and decoding of messages using an LDPC FEC scheme. Decoding algorithms used for LDPC codes require large amounts of data to be processed in a short time. For this reason, the ability of FPGAs to process large amounts of data in parallel is highly desirable in real time communication systems.

Using the Xilinx System Generator tools along with Simulink, an LDPC system could be quickly prototyped on FPGAs. Xilinx System Generator tools allow developers to construct systems using specialized blocksets within the Simulink environment.

1.2 Project Description

This project was initially broken down into three phases. In phase 1, the goal was to gain a good understanding of LDPC codes and decoding techniques by implementing a system simulation using MATLAB code as well as a Simulink model. Figure 2 depicts a high level block diagram of a coding system.

Message bits/block

LDPC Encoder

Channel

LDPC Decoder

Figure 2: High level LDPC System Block Diagram

Recovered Message

In phase 2, the goal was to break down the Simulink model into the most fundamental blocks available. It would allow for an easier transition, that is, by using Xilinx System Generator blocks, to construct an encoder and decoder for FPGA

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implementation. The Simulink model created in phase 1 is used to verify the design in Xilinx System Generator. Finally, in phase 3 of this project, the Xilinx encoder and decoder developed in phase 2 would be ported to an FPGA. The performance of the FPGA LDPC code system will be compared with simulation results from phase 1. Specifications such as bit rate, channel bandwidth requirements, and error detection capability will then be analyzed.

LDPC codes with a larger size have a better error correction performance with much higher cost of hardware implementation. In this project, LDPC codes with a relatively small block size are chosen for System Generator design on FPGA.

1.3 Linear Block Coding

LDPC codes stem from another type of FEC scheme called linear block codes [4]. To describe how LDPC codes operate, consider how typical linear block codes operate. Hamming code is given as an example. Figure 2 illustrates how a Hamming Code system operates.

Transmitter

G

m

(encoder

matrix)

Channel

Receiver

e

u +

r

+

u'

Remove Parity bits

m'

r

H' (decoder matrix)

S

Error Lookup Table

e

m = message bit word u = code word r = received code word with error S = syndrome u' = corrected code word m' = received message word

Figure 3: Hamming Code Block diagram

To describe linear block codes, (n,k) notation is commonly used. The k value denotes the number of bits in a message and the n value denotes the number of bits in the

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