PDF Memory in SystemVerilog
Memory in SystemVerilog
Prof. Stephen A. Edwards
Columbia University
Spring 2015
Implementing Memory
Memory = Storage Element Array + Addressing
Bits are expensive They should dumb, cheap, small, and tighly packed
Bits are numerous Can't just connect a long wire to each one
Williams Tube
CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits.
Mercury acoustic delay line
Used in the EDASC, 1947. 32 ? 17 bits
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