Class 21: Testing and Yield - University of Kentucky

[Pages:15]Class 21: Testing and Yield

Topics: 1. Intro 2. Motivation for Test 3. Functional vs. Manufacturing Tests 4. Testing Sequence 5. Testing Sequence 6. Testing Sequence 7. Manufacturing Tests and Yield 8. Yield vs. Area and DD 9. Yield vs. Process 10. Fault Models 11. Fault Models 12. Fault Models 13. Fault Models 14. IDDQ 15. JTAG a.k.a. Boundary Scan

1

Joseph A. Elias, PhD

Class 21: Testing and Yield

Motivation for Test (Weste, c.7)

Testing of a chip can occur at the following stages: 1) wafer level 2) package chip level 3) board level 4) system level 5) in the field

Approximate cost (1986 $s) to a company to detect a fault (total cost/total chips)

1) wafer :

$0.01 $0.10

2) package:

$0.10 $1.00

3) board:

$1.00 $10

4) system:

$10

$100

5) field:

$100 $1000

Thus the motivation to test early to avoid expensive debug effort and to avoid what consequence?

2

Joseph A. Elias, PhD

Class 21: Testing and Yield

Functional vs. Manufacturing Tests (Weste, c.7)

Functional tests refer to tests done to verify a variety of requirements: 1) verbal (customer to supplier) 2) high level test language description (ex., C) 3) hardware description language (ex., VHDL) 4) look-up table 5) a detailed spec which describes what is expected, at what test conditions

Which is probably the best one to choose?

Manufacturing tests refer to tests done before parts reach the customer, and are related to known physical causes: 1) shorts (ex., inter- and intra-layer) 2) opens (ex., missing features, such as metal lines, contacts, diffusions)

These will manifest themselves as: o nodes shorted from power to ground o nodes shorted to each other o inputs floating, outputs not connected

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Joseph A. Elias, PhD

Class 21: Testing and Yield

Testing Sequence (Weste, c.7)

A basic overview of how and when a wafer/chip gets tested: (1) Parametric, a.k.a., ETEST, PCM o In-Line: refers to testing at a wafer level, while the wafer is physically within the fab for items such as gate poly width, metal-to-metal shorting, contact resistance, and first pass transistor performance. These are located in the scribe line area.

o End-of-Line: refers to testing at a wafer level, while the wafer is physically within the fab, for an entire suite of test sites. These are located in the scribe line area.

Individual test structure

Scribe

line

Die

area

100um

mm's to cm's

4

Joseph A. Elias, PhD

Class 21: Testing and Yield

Testing Sequence (Weste, c.7)

A basic overview of how and when a wafer/chip gets tested: (2) Functional, a.k.a., full chip, first memory test o Memory testing: done on SRAM, DRAM, EEPROM, and/or FLASH portions of chip. In order to test memory by itself, test modes are usually done as part of the design. This will test the functionality of the addressing as well as a defect density monitor

o Logic Testing: done on the entire chip, which accesses the internal circuitry (issues such as addressing, logic patterns, speed are exercised). Can be done in a variety of ways, one of which is JTAG (covered later)

Scribe line area

32k x 16 FLASH

4k x16 SRAM

Memory

Logic Memory

5

Joseph A. Elias, PhD

Class 21: Testing and Yield

Testing Sequence (Weste, c.7)

A basic overview of how and when a wafer/chip gets tested: (3) Package, board, system, field o Package is done by the supplier; demonstrates initial package integrity o Board level takes into account PCB issues, such as handshaking, RC delays, etc. o System level tests whether the chip boots Unix, for example, on a microprocessor o Field is using the chip in the actual end user's configuration, for example, on the engine block of a Cadillac.

32k x 16

FLASH

4k x16 SRAM

Die

Package

Joseph A. Elias, PhD

Board

6

Class 21: Testing and Yield

Manufacturing Tests and Yield (Weste, c.7)

Yield at the wafer level is defined as The yield is dependent on area and

defect density, as shown in one form:

Another model for yield is

Yield is also a function of "killer" design or parametric issues Binning sorts the yield into buckets, or bins Parametric vs. Functional yield

7

Joseph A. Elias, PhD

Class 21: Testing and Yield

Yield vs. Area and DD

Yield

Yield

0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00

0.00

Yield vs. Area (cm2)

2.00 4.00 6.00 8.00 10.00 12.00 Area (cm2)

Yield vs. DD (cm-2)

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

0

0.2

0.4

0.6

0.8

1

1.2

DD (cm-2)

?Bigger chips yield lower, all else being equal

?Decreasing DD dramatically improves yield ?Defect density limited yield is as good as one

can achieve.

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Joseph A. Elias, PhD

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